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FUJITSU SEMICONDUCTOR DATA SHEET
DS07-13711-1E
16-Bit Original Microcontroller
CMOS
F2MC-16LX MB90420G/5G (A) Series
MB90423G/423GA/F423G/F423GA/V420G MB90427G/427GA/428G/428GA/F428G/F428GA
s DESCRIPTIONS
The FUJITSU MB90420G/5G (A) Series is a 16-bit general purpose high-capacity microcontroller designed for vehicle meter control applications etc. The instruction set retains the same AT architecture as the FUJITSU original F2MC-8L and F2MC-16L series, with further refinements including high-level language instructions, expanded addressing mode, enhanced (signed) multipler-divider computation and bit processing. In addition, A 32-bit accumulator is built in to enable long word processing.
s FEATURES
* 16-bit input capture (4 channels) Detects rising, falling, or both edges. 16-bit capture register x 4 Pin input edge detection latches the 16-bit free-run timer counter value, and generates an interrupt request. * 16-bit reload timer (2 channels) 16-bit reload timer operation (select toggle output or one-shot output) Event count function selection provided
(Continued)
s PACKAGES
Plastic QFP, 100-pin Plastic LQFP, 100-pin
(FPT-100P-M06)
(FPT-100P-M05)
MB90420G/5G (A) Series
* Clock timer (main clock) Operates directly from oscillator clock. Compensates for oscillator deviation Read/write enabled second/minute/hour register Signal interrupt * 16-bit PPG (3 channels) Output pins (3) , external trigger input pin (1) Output clock frequencies : fCP, fCP/22, fCP/24, fCP/26 * Delay interrupt Generates interrupt for task switching. Interruptions to CPU can be generated/deleted by software setting. * External interrupts (8 channels) 8-channel independent operation Interrupt source setting available : "L" to "H" edge/ "H" to "L" edge/ "L" level/ "H" level. * A/D converter 10-bit or 8-bit resolution x 8 channels (input multiplexed) Conversion time : 6.13 s or less (at fCP = 16 MHz) External trigger startup available (P50/INT0/ADTG) Internal timer startup available (16-bit reload timer 1) * UART (2 channels) Full duplex double buffer type Supports asynchronous/synchronous transfer (with start/stop bits) Internal timer can be selected as clock (16-bit reload timer 0) Asynchronous : 4808 bps, 5208 bps, 9615 bps, 10417 bps, 19230 bps, 38460 bps, 62500 bps, 500000 bps Synchronous : 500 Kbps, 1Mbps, 2Mbps (at fCP = 16 MHz) * CAN interface *1 Conforms to CAN specifications version 2.0 Part A and B. Automatic resend in case of error. Automatic transfer in response to remote frame. 16 prioritized message buffers for data and messages for data and ID Multiple message support Receiving filter has flexible configuration : All bit compare/all bit mask/two partial bit masks Supports up to 1 Mbps CAN WAKEUP function (connects RX internally to INT0) * LCD controller/driver (1 channel) Segment driver and command driver with direct LCD panel (display) drive capability * Low voltage/Program Looping detect reset *2 Automatic reset when low voltage is detected Program Looping detection function * Stepping motor controller (4 channels) High current output for all channels x 4 Synchronized 8/10-bit PWM for all channels x 2 * Sound generator 8-bit PWM signal mixed with tone frequency from 8-bit reload counter. PWM frequencies : 62.5 kHz, 31.2 kHz, 15.6 kHz, 7.8 kHz (at fCP = 16MHz) Tone frequencies : 1/2 PWM frequency, divided by (reload frequency +1) (Continued)
2
MB90420G/5G (A) Series
(Continued) * Input/output ports Push-pull output and Schmitt trigger input Programmable in bit units for input/output or peripheral signals. * Flash memory Supports automatic programming, Embeded AlgorithmTM, write/erase/erase pause/erase resume instructions Flag indicates algorithm completion Minato Electronics flash writer Boot block configuration Erasable by blocks Block protection by external programming voltage
*1 : MB90420G (A) series has 2 channels built-in, MB90425G (A) series has 1 channel built-in *2 : Built-in to MB90420GA/5GA series only. Not built-in to MB90420G/5G series. Embeded Algorithm is a registered trademark of Advanced Micro Devices Inc.
3
MB90420G/5G (A) Series
s PRODUCT LINEUP
* MB90420G (A) Series Part number MB90V420G Parameter Configuration CPU System clock ROM RAM CAN interface Low voltage/ CPU operation detection reset Packages Emulator dedicated power supply* No PGA-256 No No Evaluation model
MB90F423G *1
MB90F423GA *1
MB90423G *2
MB90423GA *2
Flash ROM model F MC-16LX CPU
2
Mask ROM model
On-chip PLL clock multiplier type ( x 1, x 2, x 3, x 4, 1/2 when PLL stopped) Minimum instruction execution time 62.5 ns (with 4 MHz oscillator x 4) External 6 KB Flash ROM 128 KB 6 KB 2 channels Yes No Yes Mask ROM 128 KB 6 KB
QFP100, LQFP100
* MB90425G (A) Series Part number MB90F428G Parameter Configuration CPU System clock ROM RAM CAN interface Low voltage/ CPU operation detection reset Packages Emulator dedicated power supply* No
MB90F428GA MB90427G*2 MB90427GA*2 MB90428G*1 MB90428GA*1 Mask ROM model F MC-16LX CPU
2
Flash ROM model
On-chip PLL clock multiplier type ( x 1, x 2, x 3, x 4, 1/2 when PLL stopped) Minimum instruction execution time 62.5 ns (with 4 MHz oscillator x 4) Flash ROM 128 KB 6 KB Mask ROM 64 KB 4 KB 1 channel Yes No Yes No
Yes
Mask ROM 128 KB 6 KB
QFP100, LQFP100
* : When used with evaluation pod MB2145-507, use DIP switch S2 setting. For details see the MB2145-507 Hardware Manual (2.7 "Emulator Dedicated Power Supply Pin") . *1 : Under development *2 : Planned
4
MB90420G/5G (A) Series
s PIN ASSIGNMENTS
(TOP VIEW)
VSS X0 X1 VCC P00/SIN0/INT4 P01/SOT0/INT5 P02/SCK0/INT6 P03/SIN1/INT7 P04/SOT1 P05/SCK1/TRG P06/PPG0/TOT1 P07/PPG1/TIN1 P10/PPG2 P11/TOT0/WOT P12/TIN0/IN3 P13/IN2 P14/IN1 P15/IN0 COM0 COM1 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100
COM2 COM3 SEG0 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 VSS SEG8 SEG9 SEG10 SEG11 P36/SEG12 P37/SEG13 P40/SEG14 P41/SEG15 P42/SEG16 P43/SEG17 P44/SEG18 VCC P45/SEG19 P46/SEG20 P47/SEG21 C P90/SEG22 P91/SEG23 V0
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
X0A X1A P57/SGA RST P56/SGO/FRCK P55/RX0 P54/TX0 DVSS P87/PWM2M3 P86/PWM2P3 P85/PWM1M3 P84/PWM1P3 DVCC P83/PWM2M2 P82/PWM2P2 P81/PWM1M2 P80/PWM1P2 DVSS P77/PWM2M1 P76/PWM2P1 P75/PWM1M1 P74/PWM1P1 DVCC P73/PWM2M0 P72/PWM2P0 P71/PWM1M0 P70/PWM1P0 DVSS P53/INT3 MD2
50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 MD1 MD0 P52/INT2 (/TX1) P51/INT1 (/RX1) P67/AN7 P66/AN6 P65/AN5 P64/AN4 VSS P63/AN3 P62/AN2 P61/AN1 P60/AN0 AVSS P50/INT0/ADTG AVRH AVCC V3 V2 V1
(FPT-100P-M06)
(Continued)
5
MB90420G/5G (A) Series
(Continued)
(TOP VIEW)
P57/SGA 76 X1A 77 X0A 78 VSS 79 X0 80 X1 81 VCC 82 P00/SIN0/INT4 83 P01/SOT0/INT5 84 P02/SCK0/INT6 85 P03/SIN1/INT7 86 P04/SOT1 87 P05/SCK1/TRG 88 P06/PPG0/TOT1 89 P07/PPG1/TIN1 90 P10/PPG2 91 P11/TOT0/WOT 92 P12/TIN0/IN3 93 P13/IN2 94 P14/IN1 95 P15/IN0 96 COM0 97 COM1 98 COM2 99 COM3 100 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 RST P56/SGO/FRCK P55/RX0 P54/TX0 DVSS P87/PWM2M3 P86/PWM2P3 P85/PWM1M3 P84/PWM1P3 DVCC P83/PWM2M2 P82/PWM2P2 P81/PWM1M2 P80/PWM1P2 DVSS P77/PWM2M1 P76/PWM2P1 P75/PWM1M1 P74/PWM1P1 DVCC P73/PWM2M0 P72/PWM2P0 P71/PWM1M0 P70/PWM1P0 DVSS
SEG0 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 VSS SEG8 SEG9 SEG10 SEG11 P36/SEG12 P37/SEG13 P40/SEG14 P41/SEG15 P42/SEG16 P43/SEG17 P44/SEG18 VCC P45/SEG19 P46/SEG20 P47/SEG21 C
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
P53/INT3 MD2 MD1 MD0 P52/INT2 (/TX1) P51/INT1 (/RX1) P67/AN7 P66/AN6 P65/AN5 P64/AN4 VSS P63/AN3 P62/AN2 P61/AN1 P60/AN0 AVSS P50/INT0/ADTG AVRH AVCC V3 V2 V1 V0 P91/SEG23 P90/SEG22
(FPT-100P-M05)
6
MB90420G/5G (A) Series
s PIN DESCRIPTIONS
Pin no. LQFP 80 81 78 77 75 83 QFP 82 83 80 79 77 85 Symbol X0 X1 X0A A X1A RST P00 SIN0 INT4 P01 84 86 SOT0 INT5 P02 85 87 SCK0 INT6 P03 86 88 SIN1 INT7 87 89 P04 SOT1 P05 88 90 SCK1 TRG P06 89 91 PPG0 TOT1 P07 90 92 PPG1 TIN1 91 93 P10 PPG2 G G G G G G G G G B Circuit type A Description High speed oscillator input pin. High speed oscillator output pin. Low speed oscillator input pin. If no oscillator is connected, apply pull-down processing. Low speed oscillator output pin. If no oscillator is connected, leave open. Reset input pin. General purpose input/output port. UART ch.0 serial data input pin. INT4 external interrupt input pin. General purpose input/output port. UART ch.0 serial data output pin. INT5 external interrupt input pin. General purpose input/output port. UART ch.0 serial clock input/output pin. INT6 external interrupt input pin. General purpose input/output port. UART ch.1 serial data input pin. INT7 external interrupt input pin. General purpose input/output port. UART ch.1 serial data output pin. General purpose input/output port. UART ch.1 serial clock input/output pin. 16-bit PPG ch.0-2 external trigger input pin. General purpose input/output port. 16-bit PPG ch.0 output pin. 16-bit reload timer ch.1 TOT output pin. General purpose input/output port. 16-bit PPG ch.1 output pin. 16-bit reload timer ch.1 TIN output pin. General purpose input/output port. 16-bit PPG ch.2 output pin.
(Continued)
7
MB90420G/5G (A) Series
Pin no. LQFP 92 QFP 94
Symbol P11 TOT0 WOT P12
Circuit type
Description General purpose input/output port.
G
16-bit reload timer ch.0 TOT output pin. Real-time clock timer WOT output pin. General purpose input/output port.
93
95
TIN0 IN3 P13 to P15 IN2 to IN0 COM0 to COM3 SEG0 to SEG11 P36 to P37 SEG12 to SEG13 P40 to P47 SEG14 to SEG21 P90 to P91 SEG22 to SEG23 P50 INT0 ADTG P60 to P67 AN0 to AN7 P51 INT1 (RX1 *) P52
G
16-bit reload timer ch.0 TIN output pin. Input capture ch.3 trigger input pin. General purpose input/output ports. Input capture ch.0-2 trigger input pins. LCD controller/driver common output pins. LCD controller/driver segment output pins. General purpose output ports.
94 to 96 97 to 100 1 to 8, 10 to 13 14 to 15
96 to 98 99 to 100, 1 to 2 3 to 10, 12 to 15 16 to 17
G I I
E
LCD controller/driver segment output pins. General purpose input output ports.
16 to 20, 22 to 24
18 to 22, 24 to 26
E
LCD controller/driver segment output pins. General purpose input output ports.
26 to 27
28 to 29
E
LCD controller/driver segment output pins. General purpose input output ports.
34
36
G
INT0 external interrupt input pin. A/D converter external trigger input pin. General purpose input output ports.
36 to 39, 41 to 44
38 to 41, 43 to 46
F
A/D converter input pins. General purpose input output port.
45
47
G
INT1 external interrupt input pin. CAN interface 1 RX intput pin. General purpose input output port.
46
48
INT2 (TX1 *) P53 INT3
G
INT2 external interrupt input pin. CAN interface 1 TX output pin. General purpose input output port. INT3 external interrupt input pin.
50
52
G
* : MB90420G (A) series only.
(Continued)
8
MB90420G/5G (A) Series
Pin no. LQFP QFP
Symbol P70 to P73
Circuit type
Description General purpose input output ports.
52 to 55
54 to 57
PWM1P0 PWM1M0 PWM2P0 PWM2M0 P74 to P77 PWM1P1 PWM1M1 PWM2P1 PWM2M1 P80 to P83 PWM1P2 PWM1M2 PWM2P2 PWM2M2 P84 to P87 PWM1P3 PWM1M3 PWM2P3 PWM2M3 P54 TX0 P55 RX0 P56 SGO FRCK P57 SGA V0 to V3 DVCC DVSS AVCC AVSS AVRH
H
Stepping motor controller ch.0 output pins.
General purpose input output ports. H
57 to 60
59 to 62
Stepping motor controller ch.1 output pins.
General purpose input output ports. H
62 to 65
64 to 67
Stepping motor controller ch.2 output pins.
General purpose input output ports. H
67 to 70
69 to 72
Stepping motor controller ch.3 output pins.
72 73
74 75
G G
General purpose input output port. CAN interface 0 TX output pin. General purpose output port. CAN interface 0 RX input pin. General purpose input output port. Sound generator SG0 output pin. Free-run timer clock input pin. General purpose input output port. Sound generator SGA output pin. LCD controller /driver reference power supply pins. High current output buffer with dedicated power supply input pins (pin numbers 54-57, 59-62, 64-67, 69-72) . High current output buffer with dedicated power supply GND pins (pin numbers 54-57, 59-62, 64-67, 69-72) . A/D converter dedicated power supply input pin. A/D converter dedicated GND supply pin. A/D converter Vref + input pin. Vref - AVss.
74
76
G
76 28 to 31 56, 66
78 30 to 33 58, 68
G
51, 61, 71 53, 63, 73 32 35 33 34 37 35
(Continued)
9
MB90420G/5G (A) Series
(Continued) Pin no.
LQFP 47 48 49 25 21, 82 QFP 49 50 51 27 23, 84
Symbol MD0 MD1 MD2 C VCC VSS
Circuit type B* D*
Description Test mode input pins. Connect to VCC. Text mode input pin. Connect to VSS. External capacitor pin. Connect an 0.1 F capacitor between this pin and VSS. Power supply input pins. GND power supply pins.
9, 40, 79 11, 42, 81
* : Type C in the flash ROM models.
10
MB90420G/5G (A) Series
s I/O CIRCUIT TYPE
Type
X1
Circuit
Remarks * Oscillation feedback resistance : approx. 1 M
A
X0
Standby control signal
* Pull-up resistance attached : approx. 50 k, hysteresis input B
Hysteresis input
* Hysteresis input C
Hysteresis input
Hyteresis input
D
* Pull-down resistance attached : approx. 50 k, hysteresis input * No pull-down resistance on flash models.
* CMOS output * LCDC output * Hysteresis input
E
LCDC output Hysteresis input
(Continued)
11
MB90420G/5G (A) Series
(Continued)
Type Circuit Remarks * CMOS output * Hysteresis input * Analog input
F
Analog input Hysteresis input
* CMOS output * Hysteresis input
G
Hysteresis input
* CMOS high current output * Hysteresis input
High current
H
Hysteresis input
* LCDC output
I
LCDC output
12
MB90420G/5G (A) Series
s HANDLING DEVICES
When handling semiconductor devices, care must be taken with regard to the following ten matters. * Strictly observe maximum rated voltages (prevent latchup) * Stable supply voltage * Power-on procedures * Treatment of unused input pins * Treatment of A/D converter power supply pins * Use of external clock signals * Power supply pins * Proper sequence of A/D converter power supply analog input * Handling the power supply for high-current output buffer pins (DVCC, DVSS) * Pull-up/pull-down resistance * Precautions when not using a sub clock signal. Precautions for Handling Semiconductor Devices * Strictly observe maximum rated voltages (prevent latchup) When CMOS integrated circuit devices are subjected to applied voltages higher than VCC at input and output pins other than medium- and high-withstand voltage pins, or to voltages lower than VSS, or when voltages in excess of rated levels are applied between VCC and VSS, a phenomenon known as latchup can occur. In a latchup condition, supply current can increase dramatically and may destroy semiconductor elements. In using semiconductor devices, always take sufficient care to avoid exceeding maximum ratings. Also care must be taken when power to analog systems is switched on or off, to ensure that the analog power supply (AVCC, AVRH, DVCC) and analog input do not exceed the digital power supply (VCC) . Once the digital power supply (VCC) is switched on, the analog power (AVCC,AVRH,DVCC) may be turned on in any sequence. * Stable supply voltage Even within the warranted operating range of VCC supply voltage, sudden fluctuations in supply voltage can cause abnormal operation. The recommended stability for ripple fluctuations (P-P values) at commercial frequencies (50 to 60 Hz) should be within 10% of the standard VCC value, and voltage fluctuations that occur during switching of power supplies etc. should be limited to transient fluctuation rates of 0.1 V/ms or less. * Power-on procedures In order to prevent abnormal operation of the internal built-in step-down circuits, voltage rise time during poweron should be attained within 50 s (0.2 V to 2.7 V) . * Treatment of unused input pins If unused input pins are left open, they may cause abnormal operation or latchup which may lead to permanent damage to the semiconductor. Any such pins should be pulled up or pulled down through resistance of at least 2 k. Also any unused input/output pins should be left open in output status, or if found set to input status, they should be treated in the same way as input pins. * Treatment of A/D converter power supply pins Even if the A/D converter is not used, pins should be connected so that AVCC = VCC, and AVSS = AVRH = VSS.
13
MB90420G/5G (A) Series
* Use of external clock signals Even when an external clock is used, a stabilization period is required following a power-on reset or release from sub clock mode or stop mode. Also, when an external clock is used it should drive only the X0 pin and the X1 pin should be left open, as shown in Figure 3.
X0 OPEN X1 MB90420G/425G (A) Series
Sample external clock connection * Power supply pins Devices are designed to prevent problems such as latchup when multiple VCC and VSS supply pins are used, by providing internal connections between pins having the same potential. However, in order to reduce unwanted radiation, and to prevent abnormal operation of strobe signals due to rise in ground level, and to maintain total output current ratings, all such pins should always be connected externally to power supplies and ground. As shown in Figure 4, all VCC power supply pins must have the same potential. All VSS power supply pins should be handled in the same way. If there are multiple VCC or VSS systems, the device will not operate properly even within the warranted operating range.
VCC VSS
VCC VSS VCC
VSS
VCC VSS
VSS
VCC
Power supply input pins (VCC/VSS)
In addition, care must be given to connecting the VCC and VSS pins of this device to a current source with as little impedance as possible. It is recommended that a bypass capacitor of 1.0 F be connected between VCC and VSS as close to the pins as possible. * Proper sequence of A/D converter power supply analog input A/D converter power (AVCC, AVRH) and analog input (AN0-AN7) must be applied after the digital power supply (VCC) is switched on. When power is shut off, the A/D converter power supply and analog input must be cut off before the digital power supply is switched on (VCC) . In both power-on and shut-off, care should be taken that AVRH does not exceed AVCC. Even when pins which double as analog input pins are used as input ports, be sure that the input voltage does not exceed AVCC. (There is no problem if analog power supplies and digital power supplies are turned off and on at the same time.) 14
MB90420G/5G (A) Series
* Handling the power supply for high-current output buffer pins (DVCC, DVSS) Always apply power to high-current output buffer pins (DVCC, DVSS) after the digital power supply (VCC) is turned on. Also when switching power off, always shut off the power supply to the high-current output buffer pins (DVCC, DVSS) before switching off the digital power supply (VCC) . (There will be no problem if high-current output buffer pins and digital power supplies are turned off and on at the same time.) Even when high-current output buffer pins are used as general purpose ports, the power for high current output buffer pins (DVCC, DVSS) should be applied to these pins. * Pull-up/pull-down resistance The MB90420G/5G series does not support internal pull-up/pull-down resistance. If necessary, use external components. * Precautions for when not using a sub clock signal. If the X0A and X1A pins are not connected to an oscillator, apply pull-down treatment to the X0A pin and leave the X1A pin open.
15
MB90420G/5G (A) Series
s BLOCK DIAGRAM
X0, X1 X0A, X1A RST
Clock control circuit
CPU F2MC-16LX core
RAM
Interrupt controller Low voltage detector reset F2MC-16LX BUS P87/PWM2M3 P86/PWM2P3 P85/PWM1M3 P84/PWM1P3 P83/PWM2M2 P82/PWM2P2 P81/PWM1M2 P80/PWM1P2 P77/PWM2M1 P76/PWM2P1 P75/PWM1M1 P74/PWM1P1 P73/PWM2M0 P72/PWM2P0 P71/PWM1M0 P70/PWM1P0
ROM
P57/SGA P56/SGO/FRCK P55/RX0 P54/TX0 P53/INT3 P52/INT2 (/TX1) P51/INT1 (/RX1) P50/INT0/ADTG P00/SIN0/INT4 P01/SOT0/INT5 P02/SCK0/INT6 P03/SIN1/INT7 P04/SOT1 P05/SCK1/TRG P06/PPG0/TOT1 P07/PPG1/TIN1
Sound generator
Port 8
CAN controller Port 5
External interrupt (8 ch) UART0/1 Prescaler 0/1
Stepping motor Controller 0/1/2/3
Port 7
Port 0 PPG0/1/2 P10/PPG2 P11/TOT0/WOT P12/TIN0/IN3 P13/IN2 P14/IN1 P15/IN0 Port 1
Port 6 P67 - P60/ AN7 - AN0 AVCC/AVSS AVRH P91 - P90/ SEG23 - SEG22 P47 - P40/ SEG21 - SEG14 P37 - P36/ SEG13 - SEG12 SEG11 - SEG0 COM3 - COM0 V3 - V0
A/D converter (8 ch)
Port 9 Reload timer 0/1 Real-time Clock timer Port 3 ICU0/1/2/3 Free-run timer
Port 4
LCD controller/ driver
Evaluation device (MB90V420G) No built-in ROM Built-in RAM is 6 KB.
16
MB90420G/5G (A) Series
s MEMORY MAP
Single chip mode (with ROM mirror function) 000000H Peripheral area 0000C0H
000100H Register RAM area Address #2
003900H Peripheral area 004000H
010000H ROM area (FF bank image) FF0000H Address #1 ROM area FFFFFFH : Internal access memory : Access prohibited
Parts No. MB90423G (A) MB90427G (A) MB90428G (A) MB90F423G (A) MB90F428G (A) MB90V420G
Address #1 FE0000H FF0000H FE0000H FE0000H FE0000H FE0000H *
Address #2 001900H 001100H 001900H 001900H 001900H 001900H
* : MB90V420G has no built-in ROM. On the tool side this area may be considered a ROM decoder.
Note : To select models without the ROM mirror function, see the "ROM Mirror Function Selection Module." The image of the ROM data in the FF bank appears at the top of the 00 bank, in order to enable efficient use of small C compiler models. The lower 16-bit address for the FF bank will be assigned to the same address, so that tables in ROM can be referenced without declaring a "far" indication with the pointer. For example when accessing the address 00C000H, the actual access is to address FFC000H in ROM. Here the FF bank ROM area exceeds 48 KB, so that it is not possible to see the entire area in the 00 bank image. Therefore because the ROM data from FF4000H to FFFFFFH will appear in the image from 004000H to 00FFFFH, it is recommended that the ROM data table be stored in the area from FF4000H to FFFFFFH. 17
MB90420G/5G (A) Series
s I/O MAP
* Other than CAN Interface Address Register name 00H 01H 02H 03H 04H 05H 06H 07H 08H 09H 0AH to 0FH 10H 11H 12H 13H 14H 15H 16H 17H 18H 19H 1AH 1BH to 1FH 20H 21H 22H 23H 24H 25H 26H 27H 28H 29H A/D control status register lower A/D control status register higher A/D data register lower A/D data register higher Compare clear register Timer data register Timer control status register lower Timer control status register higher Port 3 direction register Port 4 direction register Port 5 direction register Port 6 direction register Port 7 direction register Port 8 direction register Port 9 direction register Analog input enable Port 0 direction register Port 1 direction register Port 3 data register Port 4 data register Port 5 data register Port 6 data register Port 7 data register Port 8 data register Port 9 data register Port 0 data register Port 1 data register Symbol PDR0 PDR1 PDR3 PDR4 PDR5 PDR6 PDR7 PDR8 PDR9 Read/write Peripheral function R/W R/W R/W R/W R/W R/W R/W R/W R/W Port 0 Port 1 Port 3 Port 4 Port 5 Port 6 Port 7 Port 8 Port 9 Initial value XXXXXXXX - - XX XX XX XX - - - - - XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX - - - - - -XX
(Disabled)
(Disabled) DDR0 DDR1 DDR3 DDR4 DDR5 DDR6 DDR7 DDR8 DDR9 ADER R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Port 0 Port 1 Port 3 Port 4 Port 5 Port 6 Port 7 Port 8 Port 9 Port 6, A/D 00000000 - - 000000 00 - - - - - 00000000 00000000 00000000 00000000 00000000 - - - - - - 00 11111111
(Disabled)
(Disabled) ADCSL ADCSH ADCRL ADCRH CPCLR TCDT TCCSL TCCSH R/W R/W R R/W R/W R/W R/W R/W R/W R/W 16-bit free-run timer A/D converter 00000000 00000000 XXXXXXXX 0 0 1 0 1 XXX XXXXXXXX XXXXXXXX 00000000 00000000 00000000 0- - 00000
(Continued)
18
MB90420G/5G (A) Series
Address 2AH 2BH 2CH 2DH 2EH 2FH 30H 31H 32H 33H 34H 35H 36H 37H 38H 39H 3AH 3BH 3CH 3DH 3EH 3FH 40H to 4FH 50H 51H 52H 53H 54H 55H 56H 57H 58H 59H
Register name PPG0 control status register lower PPG0 control status register higher PPG1 control status register lower PPG1 control status register higher PPG2 control status register lower PPG2 control status register higher External interrupt enable External interrupt request External interrupt level lower External interrupt level higher Serial mode register 0 Serial control register 0 Input data register 0/ Output data register 0 Serial status register 0 Serial mode register 1 Serial control register 1 Input data register 1/ Output data register 1 Serial status register 1 Clock division control register 0 CAN wake-up control register Clock division control register 1
Symbol PCNTL0 PCNTH0 PCNTL1 PCNTH1 PCNTL2 PCNTH2 ENIR EIRR ELVRL ELVRH SMR0 SCR0 SIDR0/ SODR0 SSR0 SMR1 SCR1 SIDR1/ SODR1 SSR1 CDCR0 CWUCR CDCR1
Read/write Peripheral function R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Real-time clock timer 16-bit reload timer 1 16-bit reload timer 0 Prescaler CAN Prescaler UART1 UART 0 External interrupt 16-bit PPG0 16-bit PPG1 16-bit PPG2
Initial value 00000000 000000000000000 000000000000000 000000000000000 XXXXXXXX 00000000 00000000 00000-00 00000100 XXXXXXXX 00001000 00000-00 00000100 XXXXXXXX 00001000 0---0000 -------0 0---0000 00000000 - - - 00000 XXXXXXXX XXXXXXXX 00000000 - - - 00000 XXXXXXXX XXXXXXXX 000- - 000 00000000
(Disabled)
Area reserved for CAN interface 0 Timer control status register 0 lower TMCSR0L Timer control status register 0 highTMCSR0H er Timer register 0/ Reload register 0 TMR0/ TMRLR0
Timer control status register 1 lower TMCSR1L Timer control status register 1 highTMCSR1H er Timer register 1/ Reload register 1 Clock timer control register lower Clock timer control register higher TMR1/ TMRLR1 WTCRL WTCRH
(Continued)
19
MB90420G/5G (A) Series
Address 5AH 5BH 5CH 5DH 5EH 5FH 60H 61H 62H 63H 64H 65H 66H 67H 68H 69H 6AH 6BH 6CH 6DH 6EH 6FH 70H to 7FH 80H 81H 82H 83H 84H 85H 86H 87H to 9DH
Register name Sound control register lower Sound control register higher Frequency data register Amplitude data register Decrement grade register Tone count register Input capture register 0 Input capture register 1 Input capture register 2 Input capture register 3 Input capture control status 0/1 Input capture control status 2/3 LCDC control register lower LCDC control register higher Low voltage detect reset control register ROM mirror
Symbol SGCRL SGCRH SGFR SGAR SGDR SGTR IPCP0 IPCP1 IPCP2 IPCP3 ICS01 ICS23 LCRL LCRH LVRC ROMM
Read/write Peripheral function R/W R/W R/W R/W R/W R/W R Input capture 0/1 R R Input capture 2/3 R R/W R/W R/W R/W R/W W Input capture 0/1 Input capture 2/3 Sound generator
Initial value 00000000 0 - - - - - 00 XXXXXXXX 00000000 XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 00000000 00000000 00010000 00000000 10111000 XXXXXXX1
(Disabled) (Disabled) LCD controller/ driver Low voltage detect reset ROM mirror Stepping motor controller0 Stepping motor controller1 Stepping motor controller2 Stepping motor controller3
Area reserved for CAN interface 1 PWM control register 0 PWC0 R/W 00000--0
(Disabled) PWM control register 1 PWC1 R/W 00000--0
(Disabled) PWM control register 2 PWC2 R/W 00000--0
(Disabled) PWM control register 3 PWC3 R/W 00000--0
(Disabled)
(Continued)
20
MB90420G/5G (A) Series
(Continued) Address
9EH 9FH A0H A1H A2H to A7H A8H A9H AAH ABH to ADH AEH AFH B0H B1H B2H B3H B4H B5H B6H B7H B8H B9H BAH BBH BCH BDH BEH BFH C0H to FFH Interrupt control register 00 Interrupt control register 01 Interrupt control register 02 Interrupt control register 03 Interrupt control register 04 Interrupt control register 05 Interrupt control register 06 Interrupt control register 07 Interrupt control register 08 Interrupt control register 09 Interrupt control register 10 Interrupt control register 11 Interrupt control register 12 Interrupt control register 13 Interrupt control register 14 Interrupt control register 15 Flash control register Watchdog control Time base timer control register Clock timer control register
Register name ROM correction control register Delay interrupt/release Power saving mode Clock select
Symbol PACSR DIRR LPMCR CKSCR
Read/write Peripheral function R/W R/W R/W R/W Address match detection function Delayed interrupt Power saving control circuit
Initial value - - - - - 0-0 -------0 00011000 11111100
(Disabled) WDTC TBTC WTC R/W R/W R/W (Disabled) FMCS ICR00 ICR01 ICR02 ICR03 ICR04 ICR05 ICR06 ICR07 ICR08 ICR09 ICR10 ICR11 ICR12 ICR13 ICR14 ICR15 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Interrupt controller Flash interface 0 0 0 X 0 XX 0 00000111 00000111 00000111 00000111 00000111 00000111 00000111 00000111 00000111 00000111 00000111 00000111 00000111 00000111 00000111 00000111 Watchdog timer Time base timer Clock timer (sub clock) XXXXX 1 1 1 1 - - 00100 1X000000
(Disabled)
(Disabled)
21
MB90420G/5G (A) Series
Address 1FF0H 1FF1H 1FF2H 1FF3H 1FF4H 1FF5H 3900H to 391FH 3920H 3921H 3922H 3923H 3924H 3925H 3926H to 3927H 3928H 3929H 392AH 392BH 392CH 392DH 392EH to 392FH 3930H 3931H 3932H 3933H 3934H 3935H 3936H to 3959H
Register name ROM correction address 0 ROM correction address 1 ROM correction address 2 ROM correction address 3 ROM correction address 4 ROM correction address 5
Symbol PADR0 PADR0 PADR0 PADR1 PADR1 PADR1
Read/write Peripheral function R/W R/W R/W R/W R/W R/W Address match detection function
Initial value XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
(Disabled) PPG0 down counter register PPG0 cycle setting register PPG0 duty setting register PDCR0 PCSR0 PDUT0 R W W 16-bit PPG 0 11111111 11111111 XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
(Disabled) PPG1 down counter register PPG1 cycle setting register PPG1 duty setting register PDCR1 PCSR1 PDUT1 R W W 16-bit PPG 1 11111111 11111111 XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
(Disabled) PPG2 down counter register PPG2 cycle setting register PPG2 duty setting register PDCR2 PCSR2 PDUT2 R W W 16 bit PPG 2 11111111 11111111 XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
(Disabled)
(Continued)
22
MB90420G/5G (A) Series
Address 395AH 395BH 395CH 395DH 395EH 395FH
Register name Sub second data register Second data register Minute data register Hour data register
Symbol WTBR WTSR WTMR WTHR VRAM
Read/write Peripheral function R/W R/W R/W R/W R/W LCD controller/ driver Real time clock timer
Initial value XXXXXXXX XXXXXXXX - - - XXXXX - - XXXXXX - - XXXXXX - - - XXXXX XXXXXXXX
3960H to LCD display RAM 396FH 3970H to 397FH 3980H 3981H 3982H 3983H 3984H 3985H 3986H to 3987H 3988H 3989H 398AH 398BH 398CH 398DH 398EH to 398FH 3990H 3991H 3992H 3993H 3994H 3995H 3996H to 3997H PWM1 compare register 2 PWM2 compare register 2 PWM1 select register 2 PWM2 select register 2 PWM1 compare register 1 PWM2 compare register 1 PWM1 select register 1 PWM2 select register 1 PWM1 compare register 0 PWM2 compare register 0 PWM1 select register 0 PWM2 select register 0
(Disabled) PWC10 PWC20 PWS10 PWS20 R/W R/W R/W R/W Stepping motor controller 0 XXXXXXXX - - - - - - XX XXXXXXXX - - - - - - XX - - 000000 -0000000
(Disabled) PWC11 PWC21 PWS11 PWS21 R/W R/W R/W R/W Stepping motor controller 1 XXXXXXXX - - - - - - XX XXXXXXXX - - - - - - XX --000000 -0000000
(Disabled) PWC12 PWC22 PWS12 PWS22 R/W R/W R/W R/W Stepping motor controller 2 XXXXXXXX - - - - - - XX XXXXXXXX - - - - - - XX --000000 -0000000
(Disabled)
(Continued)
23
MB90420G/5G (A) Series
(Continued) Address
3998H 3999H 399AH 399BH 399CH 399DH 399EH to 39FFH 3A00H to 3AFFH 3B00H to 3BFFH 3C00H to 3CFFH 3D00H to 3DFFH 3E00H to 3EFFH
Register name PWM1 compare register 3 PWM2 compare register 3 PWM1 select register 3 PWM2 select register 3
Symbol PWC13 PWC23 PWS13 PWS23
Read/write Peripheral function R/W R/W R/W R/W Stepping motor controller 3
Initial value XXXXXXXX - - - - - - XX XXXXXXXX - - - - - - XX --000000 -0000000
(Disabled) Area reserved for CAN interface 0 Area reserved for CAN interface 1 Area reserved for CAN interface 0 Area reserved for CAN interface 1 (Disabled)
* Initial value symbols : "0" initial value 0. "1" initial value 1. "X" initial value undetermined "-" initial value undetermined (none) * Write/read symbols : "R/W" read/write enabled "R" read only "W" write only * Addresses in the area 0000H to 00FFH are reserved for the principal functions of the MCU. Read access attempts to reserved areas will result in an "X" value. Also, write access to reserved areas is prohibited.
24
MB90420G/5G (A) Series
* I/O Map for CAN Interface Address CAN0 000040H 000041H 000042H 000043H 000044H 000045H 000046H 000047H 000048H 000049H 00004AH 00004BH 00004CH 00004DH 00004EH 00004FH 003C00H 003C01H 003C02H 003C03H 003C04H 003C05H 003C06H 003C07H 003C08H 003C09H CAN1 000070H 000071H 000072H 000073H 000074H 000075H 000076H 000077H 000078H 000079H 00007AH 00007BH 00007CH 00007DH 00007EH 00007FH 003D00H 003D01H 003D02H 003D03H 003D04H 003D05H 003D06H 003D07H 003D08H 003D09H
Register name
Symbol BVALR TREQR TCANR TCR RCR RRTRR ROVRR RIER CSR LEIR RTEC BTR IDER TRTRR RFWTR TIER
Read/ write (R/W) (R/W) (W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W, R) (R/W) (R) (R/W) (R/W) (R/W) (R/W) (R/W)
Initial value 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00---000 -------0----0-1 000-0000
Message buffer valid area Transmission request register Transmission cancel register Transmission completed register Receiving completed register Remote request receiving register Receiving overrun register Receiving interrupt enable register Control status register Last event indicator register RX/TX error counter Bit timing register IDE register Transmission RTR register Remote frame receiving wait register Transmission interrupt enable register
00000000 00000000 -1111111 11111111 XXXXXXXX XXXXXXXX
003C0AH 003D0AH 003C0BH 003D0BH 003C0CH 003D0CH 003C0DH 003D0DH 003C0EH 003D0EH 003C0FH 003D0FH
00000000 00000000 XXXXXXXX XXXXXXXX
00000000 00000000
(Continued)
25
MB90420G/5G (A) Series
Address CAN0 003C10H 003C11H 003C12H 003C13H 003C14H 003C15H 003C16H 003C17H 003C18H 003C19H CAN1 003D10H 003D11H 003D12H 003D13H 003D14H 003D15H 003D16H 003D17H 003D18H 003D19H
Register name
Symbol
Read/ write
Initial value XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
Acceptance mask select register
AMSR
(R/W) XXXXXXXX XXXXXXXX
Acceptance mask register 0
AMR0
(R/W) XXXXX- - XXXXXXXX
003C1AH 003D1AH 003C1BH 003D1BH 003A00H to 003A1FH 003A20H 003A21H 003A22H 003A23H 003A24H 003A25H 003A26H 003A27H 003A28H 003A29H
Acceptance mask register 1
AMR1
(R/W) XXXXX- - -
003B00H to General purpose RAM 003B1FH 003B20H 003B21H 003B22H 003B23H 003B24H 003B25H 003B26H 003B27H 003B28H 003B29H ID register 2 ID register 1 ID register 0
(R/W)
XXXXXXXX to XXXXXXXX
XXXXXXXX IDR0 (R/W) XXXXX- - XXXXXXXX IDR1 (R/W) XXXXX- - XXXXXXXX IDR2 (R/W) XXXXX- - XXXXXXXX ID register 3 IDR3 (R/W) XXXXX- - XXXXXXXX ID register 4 IDR4 (R/W) XXXXX- - -
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
003A2AH 003B2AH 003A2BH 003B2BH 003A2CH 003B2CH 003A2DH 003B2DH 003A2EH 003B2EH 003A2FH 003A30H 003A31H 003A32H 003A33H 003B2FH 003B30H 003B31H 003B32H 003B33H
(Continued)
26
MB90420G/5G (A) Series
Address CAN0 003A34H 003A35H 003A36H 003A37H 003A38H 003A39H CAN1 003B34H 003B35H 003B36H 003B37H 003B38H 003B39H
Register name
Symbol
Read/ write
Initial value XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
ID register 5
IDR5
(R/W) XXXXX- - XXXXXXXX
003A3AH 003B3AH 003A3BH 003B3BH 003A3CH 003B3CH 003A3DH 003B3DH 003A3EH 003B3EH 003A3FH 003A40H 003A41H 003A42H 003A43H 003A44H 003A45H 003A46H 003A47H 003A48H 003A49H 003B3FH 003B40H 003B41H 003B42H 003B43H 003B44H 003B45H 003B46H 003B47H 003B48H 003B49H
ID register 6
IDR6
(R/W) XXXXX- - XXXXXXXX
ID register 7
IDR7
(R/W) XXXXX- - XXXXXXXX
ID register 8
IDR8
(R/W) XXXXX- - XXXXXXXX
ID register 9
IDR9
(R/W) XXXXX- - XXXXXXXX
003A4AH 003B4AH 003A4BH 003B4BH 003A4CH 003B4CH 003A4DH 003B4DH 003A4EH 003B4EH 003A4FH 003A50H 003A51H 003A52H 003A53H 003B4FH 003B50H 003B51H 003B52H 003B53H
ID register 10
IDR10
(R/W) XXXXX- - XXXXXXXX
ID register 11
IDR11
(R/W) XXXXX- - XXXXXXXX
ID register 12
IDR12
(R/W) XXXXX- - -
(Continued)
27
MB90420G/5G (A) Series
Address CAN0 003A54H 003A55H 003A56H 003A57H 003A58H 003A59H CAN1 003B54H 003B55H 003B56H 003B57H 003B58H 003B59H
Register name
Symbol
Read/ write
Initial value XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX - - - -XXXX - - - -XXXX - - - -XXXX - - - -XXXX - - - -XXXX - - - -XXXX - - - -XXXX - - - -XXXX - - - -XXXX - - - -XXXX - - - -XXXX
ID register 13
IDR13
(R/W) XXXXX- - XXXXXXXX
003A5AH 003B5AH 003A5BH 003B5BH 003A5CH 003B5CH 003A5DH 003B5DH 003A5EH 003B5EH 003A5FH 003A60H 003A61H 003A62H 003A63H 003A64H 003A65H 003A66H 003A67H 003A68H 003A69H 003B5FH 003B60H 003B61H 003B62H 003B63H 003B64H 003B65H 003B66H 003B67H 003B68H 003B69H
ID register 14
IDR14
(R/W) XXXXX- - XXXXXXXX
ID register 15
IDR15
(R/W) XXXXX- - -
DLC register 0 DLC register 1 DLC register 2 DLC register 3 DLC register 4 DLC register 5 DLC register 6 DLC register 7 DLC register 8 DLC register 9 DLC register 10
DLCR0 DLCR1 DLCR2 DLCR3 DLCR4 DLCR5 DLCR6 DLCR7 DLCR8 DLCR9 DLCR10
(R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W)
- - - -XXXX - - - -XXXX - - - -XXXX - - - -XXXX - - - -XXXX - - - -XXXX - - - -XXXX - - - -XXXX - - - -XXXX - - - -XXXX - - - -XXXX
003A6AH 003B6AH 003A6BH 003B6BH 003A6CH 003B6CH 003A6DH 003B6DH 003A6EH 003B6EH 003A6FH 003A70H 003A71H 003A72H 003A73H 003A74H 003A75H 003B6FH 003B70H 003B71H 003B72H 003B73H 003B74H 003B75H
(Continued)
28
MB90420G/5G (A) Series
Address CAN0 003A76H 003A77H 003A78H 003A79H CAN1 003B76H 003B77H 003B78H 003B79H
Register name DLC register 11 DLC register 12 DLC register 13 DLC register 14 DLC register 15
Symbol DLCR11 DLCR12 DLCR13 DLCR14 DLCR15
Read/ write (R/W) (R/W) (R/W) (R/W) (R/W)
Initial value - - - -XXXX - - - -XXXX - - - -XXXX - - - -XXXX - - - -XXXX - - - -XXXX - - - -XXXX - - - -XXXX - - - -XXXX - - - -XXXX
003A7AH 003B7AH 003A7BH 003B7BH 003A7CH 003B7CH 003A7DH 003B7DH 003A7EH 003B7EH 003A7FH 003A80H to 003A87H 003A88H to 003A8FH 003A90H to 003A87H 003A98H to 003A9FH 003B7FH
003B80H to Data register 0 (8 bytes) 003B87H 003B88H to Data register 1 (8 bytes) 003B8FH 003B90H to Data register 2 (8 bytes) 003B97H 003B98H to Data register 3 (8 bytes) 003B9FH
DTR0
(R/W)
XXXXXXXX to XXXXXXXX
DTR1
(R/W)
XXXXXXXX to XXXXXXXX
DTR2
(R/W)
XXXXXXXX to XXXXXXXX
DTR3
(R/W)
XXXXXXXX to XXXXXXXX
003AA0H 003BA0H to to Data register 4 (8 bytes) 003AA7H 003BA7H 003AA8H 003BA8H to to Data register 5 (8 bytes) 003AAFH 003BAFH 003AB0H 003BB0H to to Data register 6 (8 bytes) 003AB7H 003BB7H 003AB8H 003BB8H to to Data register 7 (8 bytes) 003ABFH 003BBFH 003AC0H 003BC0H to to Data register 8 (8 bytes) 003AC7H 003BC7H 003AC8H 003BC8H to to Data register 9 (8 bytes) 003ACFH 003BCFH
DTR4
(R/W)
XXXXXXXX to XXXXXXXX
DTR5
(R/W)
XXXXXXXX to XXXXXXXX
DTR6
(R/W)
XXXXXXXX to XXXXXXXX
DTR7
(R/W)
XXXXXXXX to XXXXXXXX
DTR8
(R/W)
XXXXXXXX to XXXXXXXX
DTR9
(R/W)
XXXXXXXX to XXXXXXXX
(Continued)
29
MB90420G/5G (A) Series
(Continued) Address
CAN0 CAN1
Register name
Symbol
Read/ write (R/W)
Initial value
003AD0H 003BD0H to to Data register 10 (8 bytes) 003AD7H 003BD7H 003AD8H 003BD8H to to Data register 11 (8 bytes) 003ADFH 003BDFH 003AE0H 003BE0H to to Data register 12 (8 bytes) 003AE7H 003BE7H 003AE8H 003BE8H to to Data register 13 (8 bytes) 003AEFH 003BEFH 003AF0H to 003AF7H 003BF0H to Data register 14 (8 bytes) 003BF7H
DTR10
XXXXXXXX to XXXXXXXX
DTR11
(R/W)
XXXXXXXX to XXXXXXXX
DTR12
(R/W)
XXXXXXXX to XXXXXXXX
DTR13
(R/W)
XXXXXXXX to XXXXXXXX
DTR14
(R/W)
XXXXXXXX to XXXXXXXX
003AF8H 003BF8H to to Data register 15 (8 bytes) 003AFFH 003BFFH
DTR15
(R/W)
XXXXXXXX to XXXXXXXX
30
MB90420G/5G (A) Series
s INTERRUPT SOURCES, INTERRUPT VECTORS, AND INTERRUPT CONTROL REGISTERS
Interrupt source Reset INT9 instruction Exception processing CAN0 RX CAN0 TX/NS CAN1 RX CAN1 TX/NS Input capture 0 DTP/external interrupt - ch 0 detected Reload timer 0 DTP/external interrupt - ch 1 detected Input capture 1 DTP/external interrupt - ch 2 detected Input capture 2 DTP/external interrupt - ch 3 detected Input capture 3 DTP/external interrupt - ch 4/5 detected PPG timer 0 DTP/external interrupt - ch 6/7 detected PPG timer 1 Reload timer 1 PPG timer 2 Real time clock timer Free-run timer over flow A/D converter conversion end Free-run timer clear Sound generator Time base timer Clock timer (sub clock) UART 1 RX UART 1 TX UART 0 RX UART 0 TX Flash memory status Delayed interrupt generator module x x x x x x x x EI2OS compatible x x x x x x x Interrupt vector Number #08 #09 #10 #11 #12 #13 #14 #15 #16 #17 #18 #19 #20 #21 #22 #23 #24 #25 #26 #27 #28 #29 #30 #31 #32 #33 #34 #35 #36 #37 #38 #39 #40 #41 #42 Address 08H FFFFDCH 09H FFFFD8H 0AH FFFFD4H 0BH FFFFD0H 0CH FFFFCCH 0DH FFFFC8H 0EH FFFFC4H 0FH FFFFC0H 10H FFFFBCH 11H 12H 13H 15H 16H 17H 19H 1AH 1BH FFFFB8H FFFFB4H FFFFB0H FFFFA8H FFFFA4H FFFFA0H FFFF98H FFFF94H FFFF90H
Interrupt control register Priority
ICR ICR00 ICR01 ICR02 ICR03 ICR04 ICR05 ICR06 ICR07 ICR08 ICR09 ICR10 ICR11 ICR12 ICR13 ICR14 ICR15
Address 0000B0H *1 0000B1H *1 0000B2H *1 0000B3H *1 0000B4H *1 0000B5H *1 0000B6H *1 0000B7H *1 0000B8H *1 0000B9H *1 0000BAH *1 0000BBH *1 0000BCH *1 0000BDH *1 0000BEH *1 0000BFH *1
*2 High
14H FFFFACH
18H FFFF9CH
1CH FFFF8CH 1DH FFFF88H 1EH 1FH 21H 22H 23H 25H 26H 27H 29H 2AH FFFF84H FFFF80H FFFF78H FFFF74H FFFF70H FFFF68H FFFF64H FFFF60H FFFF58H FFFF54H
20H FFFF7CH
24H FFFF6CH
28H FFFF5CH
Low 31
MB90420G/5G (A) Series
: Compatible, with EI2OS stop function : Compatible : Compatible when interrupt sources sharing ICR are not in use x : Not compatible *1 : * Peripheral functions sharing the ICR register have the same interrupt level. * If peripheral functions sharing the ICR register are using expanded intelligent I/O services, one or the other cannot be used. * When peripheral functions are sharing the ICR register and one specifies expanded intelligent I/O services, the interrupt from the other function cannot be used. *2 : Priority applies when interrupts of the same level are generated.
32
MB90420G/5G (A) Series
s PERIPHERAL FUNCTIONS
1. I/O Ports
The I/O ports function is to send data from the CPU to be output from I/O pins and load input signals at the I/O pins into the CPU, according to the port data register (PDR) . Port input/output at I/O pins can be controlled in bit units by the port direction register (DDR) as required. The following list shows each of the functions as well as the shared peripheral function for each port. * * * * * * * * * Port 0 : General purpose I/O port, shared with peripheral functions (external interrupt/UART/PPG) Port 1 : General purpose I/O port, shared with peripheral functions (PPG/reload timer/clock timer/ICU) Port 3 : General purpose I/O port, shared with peripheral functions (LCD) Port 4 : General purpose I/O port, shared with peripheral functions (LCD) Port 5 : General purpose I/O port, shared with peripheral functions (External interrupt/CAN/SG) Port 6 : General purpose I/O port, shared with peripheral functions (A/D converter) Port 7 : General purpose I/O port, shared with peripheral functions (Stepping motor controller) Port 8 : General purpose I/O port, shared with peripheral functions (Stepping motor controller) Port 9 : General purpose I/O port, shared with peripheral functions (LCD) Input format Output format
(1) List of Functions Port Pin name Function General purpose I/O port P00/SIN0/INT4 Port 0 to P07/PPG1 Peripheral function General purpose I/O port P10/PPG2 to Port 1 P15/IN0 P36/SEG12 to P37/SEG13 P40/SEG14 to P47/SEG21 CMOS (hysteresis) Peripheral function General purpose I/O port Peripheral function General purpose I/O port Peripheral function CMOS General purpose I/O port Peripheral function Analog CMOS (hysteresis) General purpose I/O port Peripheral function General purpose I/O port Peripheral function CMOS (hysteresis) General purpose I/O port Peripheral function General purpose I/O port Peripheral function bit15 P37 P57 SGA P77
PWM2M1
bit14 P36 P56 SGO FRCK P76
PWM2P1
bit13 P15 IN0 P55 RX0 P75
PWM1M1
bit12 P14 IN1 P54 TX0 P74
PWM1P1
Port 3 Port 4
SEG13 SEG12
P50/INT0 to Port 5 P57/SGA P60/AN0 to P67/AN7 P70/PWM1P0 to P77/PWM2M1 P80/PWM1P2 to P87/PWM2M3 P90/SEG22 to P91/SEG23
Port 6
Port 7 Port 8 Port 9

33
MB90420G/5G (A) Series
(Continued) Port bit11
Port 0 P13 Port 1 IN2 Port 3 Port 4 P53 Port 5 INT3 Port 6 Port 7 Port 8 Port 9 P73
PWM2M0
bit10 P12 IN3 TIN0 P52 INT2 TX1 P72
PWM2P0
bit9 P11 WOT TOT0 P51 INT1 RX1 P71
PWM1M0
bit8 P10 PPG2 P50 INT0 P70
PWM1P0
bit7 P07 PPG1 TIN1 P47 P67 AN7 P87
PWM2M3
bit6 P06 PPG0 TOT1 P46 P66 AN6 P86
PWM2P3
bit5 P05 SCK1 P45 P65 AN5 P85
PWM1M3
bit4 P04 SOT1 P44 P64 AN4 P84
PWM1P3
bit3 P03 SIN1 INT7 P43 P63 AN3 P83
PWM2M2
bit2 P02 SCK0 INT6 P42 P62 AN2 P82
PWM2P2
bit1 P01 SOT0 INT5 P41 P61 AN1 P81
PWM1M2
bit0 P00 SIN0 INT4 P40 P60 AN0 P80
PWM1P2
SEG21 SEG20 SEG19 SEG18 SEG17 SEG16 SEG15 SEG14

P91
P90

SEG23 SEG22
Note : Port 6 also functions as an analog input pin. When using this port as a general purpose port, always write "0" to the corresponding analog input enable register (ADER) bit. The ADER bit is initialized to "1" at reset.
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MB90420G/5G (A) Series
(2) Block Diagrams
Ports 0, 1, 3, 4, 5, 7, 8, 9 Peripheral function output Peripheral function input Peripheral function output enabled PDR (Port data register) Internal data bus
PDR read Output latch PDR write Pin DDR (Port direction register) Direction latch DDR write
DDR read Standby control (SPL = 1) or LCD output enabled
Port 6 ADER PDR (Port data register) Internal data bus Analog input
RDR read Output latch PDR write Pin
DDR (Port direction register) Direction latch DDR write
DDR read Standby control (SPL = 1)
35
MB90420G/5G (A) Series
2. Watchdog Timer/Time Base Timer/Clock Timer
The watchdog timer, timer base timer, and clock timer have the following circuit configuration. * Watchdog timer : Watchdog counter, control register, watchdog reset circuit * Time base timer : 18-bit timer, interval interrupt control circuit * Clock timer : 15-bit timer, interval interrupt control circuit (1) Watchdog timer function The watchdog timer is composed of a 2-bit watchdog counter that uses the carry signal from the 18-bit time base timer or 15-bit clock timer as a clock source, plus a control register and watchdog reset control circuit. After startup, this function will reset the CPU if not cleared within a given time. (2) Time base timer function The time base timer is an 18-bit free-run counter (time base counter) synchronized with the internal count clock (base oscillator divided by 2) , with an interval timer function providing a selection of four interval times. Other functions include a timer output for an oscillator stabilization wait time and clock feed to the watchdog timer or other operating clocks. Note that the time base timer uses the main clock regardless of the setting of the MCS bit or SCS bit in the CKSCR register. (3) Clock timer function The clock timer provides functions including a clock source for the watchdog timer, a sub clock base oscillator stabilization wait timer, and an interval timer to generate an interrupt at fixed intervals. Note that the clock timer uses the sub clock regardless of the setting of the MCS bit or SCS bit in the CKSCR register.
36
MB90420G/5G (A) Series
* Block Diagram
TBTC TBC1 TBC0 TBR TBIE TBOF AND Q S R 211 213 216 218 TBTRES
Main base oscillator divided by 2 Clock input Time base timer
211 213 216 218
Selector
Time base interrupt
WDTC WT1
Selector
WT0 WTE WTC
2-bit counter OF
CLR
Watchdog reset generator circuit
CLR
To WDGRST internal reset generator circuit
F2MC-16LX bus
WDCS SCE WTC2 WTC0 WTR WTIE WTOF
AND S R
SGW Power-on reset, sub-clock stop
28 29 210 211 212 213 214 216 WTRES 210 213 214 216
Q
Selector
Clock timer
AND
Q
S R
Clock input Sub base oscillator divided by 4
Clock interrupt
WDTC PONR
From power-on generator
WRST ERST SRST
RST pin From RST bit in STBYC register
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MB90420G/5G (A) Series
3. Input Capture
This circuit is composed of a 16-bit free-run timer and four 16-bit input capture circuits. (1) Input capture ( x 4) The input capture circuits consist of four independent external input pins and corresponding capture registers and control registers. When the specified edge of the external signal input (at the input pin) is detected, the value of the 16-bit free-run timer is saved in the capture register, and at the same time an interrupt can also be generated. * The valid edge (rising edge, falling edge, both edges) of the external signal can be selected. * The four input capture circuits can operate independently. * The interrupt can be generated from the valid edge of the external input signal. (2) 16-bit free-run timer ( x 1) The 16-bit free-run timer is composed of a 16-bit up-counter, control register, 16-bit compare register, and prescaler. The output values from this counter are used as the base time for the input capture circuits. * The counter clock operation can be selected from 8 options. The eight internal clock settings are , /2, /4, /8, /16, /32, /64, /128 where represents the machine clock cycle. * Interrupts can be generated from overflow events, or from compare match events with the compare register. (Compare match operation requires a mode setting.) * The counter value can be initialized to "0000H" by a reset, soft clear, or a compare match with the compare register. (3) Block diagram
interrupt #31 (1FH) IVF IVFE STOP MODE SCLR CLK2 CLK1 CLK0
Divider Clock
16-bit free-run timer
16-bit compare clear register F2MC-16LX bus
Compare circuit MSI3 0 ICLR ICRE
Interrupt #33 (21H)
A/D startup Edge detection Capture data register 0/2 EG11 EG10 EG01 EG00 IN0/2
Capture data register 1/3 ICP0 ICP1
Edge detection ICE0 ICE1
IN1/3
Interrupt #19, #23 Interrupt #15, #21
38
MB90420G/5G (A) Series
4. 16-bit Reload Timer
The 16-bit reload timer can either count down in synchronization with three types of internal clock signals in internal clock mode, or count down at the detection of the designated edge of an external signal. The user may select either function. This timer defines a transition from 0000H to FFFFH as an underflow event. Thus an underflow occurs when counting from the value [Reload register setting + 1]. A selection of two counter operating modes are available. In reload mode, the counter is reset to the count value and continues counting after an underflow, and in one-shot mode the count stops after an underflow. The counter can generate an interrupt when an underflow occurs, and is compatible with the expanded intelligent I/O services (EI2OS) . (1) 16-bit Reload timer operating modes Clock mode Counter mode Reload mode Internal clock mode Event count mode (external clock mode) (2) Internal clock mode One of three input clocks is selected as the count clock, and can be used in one of the following operations. * Soft trigger operation When "1" is written to the TRG bit in the timer control status register (TMCSR0/1) , the count operation starts.Trigger input at the TRG bit is normally valid with an external trigger input, as well as an external gate input. * External trigger operation Count operation starts when a selected edge (rising, falling, both edges) is input at the TIN0/1 pin. * External gate input operation Counting continues as long as the selected signal level ("L" or "H") is input at the TIN0/1 pin. (3) Event count mode (External clock mode) In this mode a down count event occurs when a selected valid edge (rising, falling, both edges) is input at the TIN0/1 pin. This function can also be used as an interval timer when an external clock with a fixed period is used. (4) Counter operation * Reload mode In down count operation, when an underflow event (transition from "0000H" to "FFFFH") occurs, the set count value is reloaded and count operation continues. The function can be used as an interval timer by generating an interrupt request at each underflow event. Also, a toggle waveform that inverts at each underflow can be output from the TOT0/1 pin. Counter clock Counter clock period Interval time 21/ (0.125 s) Internal clock External clock 2 / (0.5 s)
3 5
16-bit reload timer operation Soft trigger operation External trigger operation External gate input operation Soft trigger operation
One-shot mode Reload mode One-shot mode
0.125 s to 8.192 ms 0.5 s to 32.768 ms 2.0 s to 131.1 ms 0.5 s or greater
2 / (2.0 s) 23/ or greater (0.5 s)
: Machine clock cycle. Figures in ( ) are values at machine clock frequency 16 MHz. 39
MB90420G/5G (A) Series
(5) One-shot mode In down count operation, the count stops when an underflow event (transition from "0000H" to "FFFFH") occurs. This function can generate an interrupt at each underflow. While the counter is operating, a rectangular wave form indicating that the count is in progress can be output form the TOT0 and TOT1 pins. (6) Block diagram
Internal data bus TMRLR0 *1 16-bit reload register Reload signal TMR0 *1 16-bit timer register (down counter) Count clock generator circuit CLK UF Reload control circuit
Machine clock
Prescaler
3
Gate input
Valid clock decision circuit CLK
Wait signal
Clear Internal clock Pins P12/TIN0 *1 Input control circuit External clock 3 Function selection 2
To UART 0, 1 *1
Clock selector Select signal
Output signal generator Inverted circuit EN
Pins P11/TOT0 *1
Operation control circuit

CSL1 CSL0 WOD2 WOD1 WOD0 OUTE OUTL RELD INTE UF CNTE TRG Interrupt request signal #17 (11h) *2 <#28 (10h)>
Timer control status register (TNGSR0) *1 *1 : Channel 0 and channel 1. Figures in < > are for channel 1. *2 : Interrupt number
40
MB90420G/5G (A) Series
5. Real Time Clock Timer
The real time clock timer is composed of a real time clock timer control register, sub second data register, second/ minute/hour data registers, 1/2 clock divider, 21-bit prescaler and second/minute/hour counters. Because the MCU oscillation frequency operates on a given real time clock timer operation, a 4 MHz frequency is assumed. The real time clock timer operates as a real world timer and provides real world time information. * Block diagram
Main oscillator clock
OE 1/2 clock divider EN 21-bit prescaler CO
OE WOT
Sub second register
UPDT
ST
Second CI EN counter LOAD 6-bit
Minute counter CO 6-bit Second/minute/hour register CO
Hour counter CO 5-bit
INTE0 INT0
INTE1 INT1
INTE2 INT2
INT3
INT3
IRQ
41
MB90420G/5G (A) Series
6. PPG Timer
The PPG timer consists of a prescaler, one 16-bit down-counter, 16-bit data register with buffer for period setting, and 16-bit compare register with buffer for duty setting, plus pin control circuits. The timer can output pulses synchronized with an externally input soft trigger. The period and duty of the output pulse can be adjusted by rewriting the values in the two 16-bit registers. (1) PWM function Programmable to output a pulse, synchronized with a trigger. Can also be used as a D/A converter with an external circuit. (2) One-shot function Detects the edge of a trigger input, and outputs a single pulse. (3) Pin control * Set to "1" at a duty match (priority) . * Reset to "0" at a counter borrow event * Has a fixed output mode to output a simple all "L" ( or "H") signal. * Polarity can be specified (4) 16-bit down counter * Select from four types of counter operation clocks. Four internal clocks (, /4, /16, /64) cycles. * The counter value can be initialized to "FFFFH" at a reset or counter borrow event. (5) Interrupt requests * Timer startup * Counter borrow event (period match) * Duty match event * Counter borrow event (period match) or duty match event (6) Multiple channels can be set to start up at an external trigger, or to restart during operation.
: Machine clock
42
MB90420G/5G (A) Series
(7) Block diagram
PCSR Prescaler 1/1 1/4 1/16 1/32 CK Load
PDUT
PSCT 16-bit down counter Start Borrow
CMP
PPG mask Machine clock S R Inversion bit Enable Trigger input P05/TRG Interrupt selection Edge detection Soft trigger Interrupt Q
PPG output
43
MB90420G/5G (A) Series
7. Delayed Interrupt Generator Module
The delayed interrupt generator module is a module that generates interrupts for task switching. This module makes it possible to use software to generate/cancel interrupt requests to the F2MC-16LX CPU. * Block diagram
F2MC-16LX bus Delayed interrupt source generate/delete decoder
Source latch
44
MB90420G/5G (A) Series
8. DTP/External Interrupt Circuit
The DTP (Data transfer peripheral) /external interrupt circuit is located between an externally connected peripheral device and the F2MC-16LX CPU and sends interrupt requests or data transfer requests generated from the peripheral device to the CPU, thereby generating external interrupt requests or starting the expanded intelligent I/O services (EI2OS) . (1) DTP/external interrupt function The DTP/external interrupt function uses a signal input from the DTP/external interrupt pin as a startup source. And it is accepted by the CPU by the same procedure as a normal hardware interrupt, and can generate an external interrupt or start the expanded intelligent I/O service (EI2OS) . When the interrupt is accepted by the CPU, if the corresponding expanded intelligent I/O service (EI2OS) is prohibited the interrupt operates as an external interrupt function and branches to an interrupt routine. If the EI2OS is permitted the interrupt functions as a DTP function, using EI2OS for automatic data transfer, then branching to an interrupt routine after the completion of the specified number of data transfers. External interrupt Input pins 8 pins (P50/INT0 to P53/INT3, P00/INT4 to P03 INT7) Request level setting register (ELVR) sets the detection level, or selected edge for each pin "H" level/ "L" level/ rising edge/falling edge input "H" level/ "L" level input DTP function
Interrupt sources
Interrupt numbers Interrupt control Interrupt flags Process selection Processing
#16 (10H) , #18 (12H) , #20 (14H) , #22 (16H) , #24 (18H) , #26 (1AH) DTP/interrupt enable register (ENIR) permits/prohibits interrupt request output DTP/interrupt enable register (EIRR) stores interrupt sources When EI2OS prohibited (ICR : ISE = 0) Branch to external interrupt processing routine When EI2OS is enabled (ICR : ISE = 1) EI2OS performs automatic data transfer, then after a specified number of cycles, branches to an interrupt routine
ICR : Interrupt control register
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MB90420G/5G (A) Series
(2) Block diagram
Request level setting register (ELVR) LB7 LA7 LB6 LA6 LB5 LA5 LB4 LA4 LB3 LA3 LB2 LA2 LB1 LA1 LB0 LA0
Pin P03/INT7 Internal data bus
Selector
Selector
Pin P50/INT0
Pin P02/INT6
Selector
Selector
Pin P51/INT1
Pin P01/INT5
Selector
Selector
Pin P52/INT2
Pin P00/INT4
Selector
Selector
Pin P53/INT3
ER7
ER6
ER5
ER4
ER3
ER2
ER1
ER0 Interrupt request number #16 (10H) #18 (12H) #20 (14H) #22 (16H) #24 (18H) #26 (1AH)
EN7
EN6
EN5
EN4
EN3
EN2
EN1
EN0
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MB90420G/5G (A) Series
9. 8/10-bit A/D Converter
The 8/10-bit A/D converter has functions for using RC sequential comparator conversion format to convert analog input voltage into 10-bit or 8-bit digital values. The input signal is selected from 8-channel analog input pins, and the conversion start can be selected from three types : by software, 16-bit reload timer 1 or a trigger input from an external signal pin. (1) 8/10-bit A/D converter functions The A/D converter takes analog voltage signals (input voltage) input at analog input pins, and converts these to digital values, providing the following features. * Minimum conversion time is 6.13 s (at machine clock frequency of 16 MHz, including sampling time) . * Minimum sampling time is 3.75 s (at machine clock 16 MHz) * The conversion method is an RC sequential conversion in comparison with a sample hold circuit. * Either 10-bit or 8-bit resolution can be selected. * The analog input pin can select from 8 channels by a program setting. * At completion of A/D conversion, an interrupt request can be generated, or EI2OS can be started. * Because the conversion data protection function operates in an interrupt enabled state, no data is lost even in continuous conversion. * The conversion start source may be selected from : software, 16-bit reload timer 1 (rising edge) , or external trigger input (falling edge) . Three conversion modes are available Conversion mode Single conversion operation Single conversion mode
Scan conversion operation
Converts multiple consecutive channels (up Converts the specified channel (1 channel to 8 channels may be specified) one time, only) one time, then stops. then stops.
Continuous conversion Converts the specified channel (1 channel Converts multiple consecutive channels (up mode only) repeatedly. to 8 channels may be specified) repeatedly. Converts multiple consecutive channels (up Converts the specified channel (1 channel to 8 channels may be specified) , however Stop conversion mode only) one time, then pauses, waits until pauses after conversion of each channel, the next start is applied. waits until the next start is applied.
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MB90420G/5G (A) Series
(2) Block diagram
AVCC AVRH AVSS
D/A converter MPX AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7
Input circuit
Sequential comparator register Comparator F2MC-16LX bus
Sample & hold circuit
Decoder
A/D data register ADCRH, L
A/D control status register, high A/D control status register, low Timer start Trigger start Prescaler ADCSH, L Operating clock
16-bit reload timer 1
P50/ADTG
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MB90420G/5G (A) Series
10. UART
The UART is a general purpose serial data communication interface for synchronous communication, or asynchronous (start-stop synchronized) communication with external devices. Functions include normal bi-directional functions, as well as master/slave type communication functions (multi-processor mode : master side only supported) . (1) UART Functions The UART is a general purpose serial data communication interface for sending and receiving of serial data with other CPU's or peripheral devices, and provides the following functions. Functions Data buffer Transfer modes Full duplex double buffer * Clock synchronous (no start/stop bits) * Clock asynchronous (start-stop synchronized) * Exclusive baud rate generator provides a selection of 8 rates * External clock input enabled * Internal clock (can use internal clock feed from 16-bit reload timer) * 7-bit (asynchronous normal mode only) * 8-bit NRZ (Non return to zero) * Framing errors * Overrun errors * Parity errors (not enabled in multiprocessor mode) * Receiving interrupt (receiving completed, receiving error detection) * Sending interrupt (sending completed) * Sending/receiving both compatible with expanded intelligent I/O services (EI2OS) 1 (master) -to-n (slave) communication enabled (only master side supported) .
Baud rate
Data length Signal type Receiving error detection
Interrupt request
Master/slave type communication function (multi-processor mode)
Note : The UART in clock synchronous transfer does not add start bits or stop bits, but transfers data only. Data length No parity 8+1*
1
Operating mode 0 1 Normal mode Multi-processor mode
Parity
Synchronization Asynchronous Asynchronous
Stop bit length 1-bit or 2-bit *2 None
7-bit or 8-bit
2 Normal mode 8 Synchronous : Setting not available *1 : "+" indicates an address/data selection bit (A/D) for communication control. *2 : In receiving only one stop bit is detected.
49
MB90420G/5G (A) Series
(2) Block diagram
Control bus Receiving interrupt signals #39 (27H) * <#37 (25H) *> Sending interrupt signals #40 (28H) * <#38 (26H) *>
Exclusive baud rate generator 16-bit reload timer Clock selector
Sending clock Receiving clock
Receiving control circuit
Sending control circuit Sending start circuit Sending bit counter Sending parity counter
Pins P02/SCK0
Start bit detection circuit Receiving bit counter Receiving parity counter
Pin P01/SOT0
Pins P00/SIN0
Receiving shift register Receiving end
Sending shift register
Sending start SODR0/1
SIDR0/1 Receiving status judging circuit
EI2OS receiving error generator circuit (to CPU) Internal data bus
SMR0/1 register
MD1 MD0 CS2 CS1 CS0 SCKE SOE
SCR0/1 register
PEN P SBL CL A/D REC RXE TXE
SSR0/1 register
PE ORE FRE RDRF TDRE BOS RIE TIE
: Interrupt number
50
MB90420G/5G (A) Series
11. CAN Controller
The CAN controller is a self-contained module within a 16-bit microcomputer (F2MC-16LX) . The CAN (controller area network) controller is the standard protocol for serial transmissions among automotive controllers and is widely used in the industry. (1) CAN controller features The CAN controller has the following features. * Conforms to CAN specifications version 2.0 A and B. Supports sending and receiving in standard frame and expanded frame format. * Supports data frame sending by means of remote frame receiving. * 16 sending/receiving message buffers 29-bit ID and 8-byte data Multi-level message buffer configuration * Supports full bit compare, full bit mask as well as partial bet mask filtering. Provides two receiving mask registers for either standard frame or expanded frame format. * Bit speed programmable from 10 KB/s to 1 MB/s (at machine clock 16 MHz) * CAN WAKE UP function * The MB90420G (A) series has a two-channel built-in CAN controller. The MB90425G (A) series has a 1channel built-in CAN controller.
51
MB90420G/5G (A) Series
(2) Block diagram
F2MC-16LX bus Machine clock PSC PR PH RSJ TOE TS RS CSR HALT NIE NT NS1,0 BTR RTEC BVALR TREQR TBFx clear Send buffer decision TBFX Data counter Prescaler 1-to-64 frequency divider Bit timing generator
TQ (operating clock) SYNC, TSEG1, TSEG2
Node status change interrupt generator
Node status change interrupt Error control Send/receive sequencer Receiving filter control
Bus state machine
IDLE, SUSPND, TX, RX, ERR, OVRLD
Error frame generator Overload frame generator ARBLOST Output driver TX
TBFX TCANR TRTRR RFWTR TCR TIER RCR RIER RRTRR ROVRR AMSR AMR0 AMR1 IDR0 ~ 15, DLCR0 ~ 15, DTR0 ~ 15, RAM LEIR 0 1 TBFx, set, clear Sending completed interrupt generator RBFx, set Receiving completed interrupt generator RBFx, TBFx, set clear RBFx set IDSEL Receiving completed interrupt Sending completed interrupt
TDLC RDLC IDSEL BITER, STFER, CRCER, FRMER, ACKER Send shift register
Stuffing CRC ACK
TDLC
generator generator
CRCER RDLC CRC generator error check STFER
Receiving shift register
Destuffing/ stuffing error check Arbitration check Bit error check Acknowledge error check Form error check
ARBLOST BITER ACKER FRMER
Receiving filter
Receiving bufferx decision RBFX
PH1 Input latch
RX
RAM address generator
RBFX, TBFX, RDLC, TDLC, IDSEL
52
MB90420G/5G (A) Series
12. LCD Controller/Driver
The LCD controller/driver has a built-in 16 x 8-bit display data memory, and controls the LCD display by means of four common outputs and 24 segment outputs. A selection of three duty outputs are available. This block can drive an LCD (liquid crystal display) panel directly. (1) LCD controller/driver functions The LCD controller/driver provides functions for directly displaying the contents of display data memory (display RAM) on the LCD panel by means of segment output and common output. * LCD drive voltage divider resistance is built-in. External divider resistance can also be connected. * Up to 4 common outputs (COM0 to COM3) and 24 segment outputs (SEG0 to SEG23) can be used. * 16-byte display data memory (display RAM) is built-in. * The duty can be selected at 1/2, 1/3, 1/4 (limited by bias setting) . * Drives the LCD directly. Bias 1/2 bias 1/3 bias : Recommended mode x : Use prohibited x 1/2 duty 1/3 duty
x
1/4 duty
x
Note : When the SEG12 to SEG23 pins have been selected as general purpose ports by the LCRH setting, they cannot be used for segment output.
53
MB90420G/5G (A) Series
(2) Block diagram
V0 V1 V2 V3 LCDC control register L (LCRL) Divider resistance
4 Time base timer output Internal data bus Prescaler Timing controller AC circuit Common driver COM0 COM1 COM2 COM3
24 Display RAM, 16 x 8 bits Segment driver
SEG0 SEG1 SEG2 SEG3 SEG4 SEG18 SEG19 SEG20 SEG21 SEG22 SEG23
LCDC control register H (LCRH) Controller Driver
54
MB90420G/5G (A) Series
13. Low voltage/Program Looping Detection Reset Circuit
The Low voltage detection reset circuit is a function that monitors power supply voltage in order to detect when a voltage drops below a given voltage level. When a low voltage condition is detected, an internal reset signal is generated. The Program Looping detection reset circuit is a count clock with a 20-bit counter that generates an internal reset signal if not cleared within a given time after startup. (1) Low voltage detection reset circuit Detection voltage 4.0 V 0.3 V When a low voltage condition is detected, the low voltage detection flag (LVRC : LVRF) is set to "1" and an internal reset signal is output. Because the low voltage detection circuit continues to operate even in stop mode, detection of a low voltage condition generates an internal reset and releases stop mode. During an internal RAM write cycle, an internal reset is generated after the completion of writing. During the output of this internal reset, the reset output from the low voltage detection circuit is suppressed. (2) Program Looping detection reset circuit The Program Looping detection reset circuit is a counter that prevents program looping. The counter starts automatically after a power-on reset, and must be continually cleared within a given time. If the given time interval elapses and the counter has not been cleared, a cause such as infinite program looping is assumed and an internal reset signal is generated. The internal reset generated form the Program Looping detection circuit has a width of 5 machine cycles. Interval duration Number of oscillation clock cycles Approx. 262 ms * 220 cycles
* : This value assumes an oscillation clock speed of 4 MHz. During recovery from standby mode the detection period is the maximum interval plus 20 s. This circuit does not operate in modes where CPU operation is stopped. The Program Looping detection reset circuit counter is cleared under any of the following conditions. 1. Writing "0" to the LVRC register CL bit 2. Internal reset 3. Main oscillation clock stop 4. Transition to sleep mode 5. Transition to time base timer mode or clock mode 6. Start of hold
55
MB90420G/5G (A) Series
(3) Block diagram
Voltage comparator circuit
VCC
- + VSS
Program Looping detection circuit Oscillation clock Counter OF Clear Noise canceller
Constant voltage source
Internal reset
RESV0 RESV0 RESV1 RESV1
CL
LVRF RESV0 CPUF
Low voltage detection reset control register (LVRC)
Internal data bus
56
MB90420G/5G (A) Series
14. Stepping Motor Controller
The stepping motor controller is composed of two PWM pulse generators, four motor drivers and selector logic circuits. The four motor drivers have a high output drive capacity and can be directly connected to the four ends of two motor coils. They are designed to operate together with the PWM pulse generators and selector logic circuits to control motor rotation. A synchronization mechanism assures synchronization of the two PWM pulse generators. * Block diagram
Machine clock OE1 CK PWM1 pulse generator EN P1 P0 PWM Selector PWM1Mn Output enable
Prescaler
PWM1Pn
PWM1 compare register
PWM1 selector register
OE2 CK SC PWM2 pulse generator CE EN PWM Load PWM2 compare register BS PWM2 select register Selector
Output enable
PWM2Pn
PWM2Mn
n:0~3
57
MB90420G/5G (A) Series
15. Sound Generator
The sound generator is composed of a sound control register, frequency data register, amplitude data register, decrement grade register, tone count register, PWM pulse generator, frequency counter, decrement counter, and tone pulse counter. * Block diagram
Clock input
Prescaler
S1
S0
8-bit PWM pulse generator CO EN PWM Reload
CI
Frequency counter CO EN Reload Frequency data register DEC
Toggle flip-flop D EN Q
1/d
Amplitude data register DEC
Decrement counter
CI CO EN OE1
SGA OE1
Decrement grade register
Blend
SGO OE2
Tone pulse counter
TONE CI CO EN
OE2
Tone count register
INTE
INT
ST IRQ
58
MB90420G/5G (A) Series
16. Address Match Detect Function
If the address setting is the same as the ROM correction address register, an INT9 instruction is executed. The ROM correction function can be implemented by processing the INT9 interrupt service routine. Two address registers are used, each with its own compare enable bit. When there is a match between the address register and program counter, and the compare enable bit is set to "1" , the INT9 instruction is forcibly executed by the CPU. * Block diagram
ROM correction address register Enable bit
Compare
Address latch
F2MC-16LX CPU core
F2MC-16LX bus
59
MB90420G/5G (A) Series
17. ROM Mirror Function Select Module
The ROM mirror function select module uses a select register setting to enable the contents of ROM allocated to the FF bank to be viewed in the 00 bank. * Block diagram
F2MC-16LX bus ROM mirror function select register
Address area FF bank 00 bank
ROM
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MB90420G/5G (A) Series
s ELECTRICAL CHARACTERISTICS
1. Absolute Maximum Ratings
Parameter Symbol VCC Power supply voltage AVCC VAVRH DVCC Input voltage Output voltage Clamp current "L"level maximum output current*2 "L"level average output current*3 "L"level maximum total output current "L"level average total output current "H"level maximum output current "H"level average output current "H"level maximum total output current "H"level average total output current Power consumption Operating temperature Storage temperature VI VO ICLAMP IOL1 IOL2 IOLAV1 IOLAV2 IOL1 IOL2 IOLAV1 IOLAV2 IOH1*
2
(VSS = AVSS = DVSS = 0 V) Rating Min. VSS - 0.3 VSS - 0.3 VSS - 0.3 VSS - 0.3 VSS - 0.3 VSS - 0.3 -2.0 -40 -55
4 3
Max. VSS + 6.0 VSS + 6.0 VSS + 6.0 VSS + 6.0 VCC + 0.3 VCC + 0.3 2.0 15 40 4 30 100 330 50 250 -15 -40 -4 -30 -100 -330 -50 -250 500 +105 +150
Unit V V V V V V mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mW C C AVCC = VCC*1
Remarks
AVCC VAVRH DVCC = VCC*1
Other than P70-P77, P80-P87 P70-77, P80-87 Other than P70-P77, P80-P87 P70-77, P80-87 Other than P70-P77, P80-P87 P70-77, P80-87 Other than P70-P77, P80-P87 P70-77, P80-87 Other than P70-P77, P80-P87 P70-77, P80-87 Other than P70-P77, P80-P87 P70-77, P80-87 Other than P70-P77, P80-P87 P70-77, P80-87 Other than P70-P77, P80-P87 P70-77, P80-87
IOH2*2 IOHAV1*3 IOHAV2* IOH1 IOH2 IOHAV1*4 IOHAV2* PD TA TSTG
*1 : Care must be taken to ensure that AVCC and DVCC do not exceed VCC at power-on etc. *2 : Maximum output current is defined as the peak value of the current of any one of the corresponding pins. *3 : Average output current is defined as the value of the average current flowing over 100 ms at any one of the corresponding pins. The "average value" can be calculated from the formula of "operating current" times "operating factor". *4 : Average total output current is defined as the value of the average current flowing over 100 ms at all of the corresponding pins. The "average value" can be calculated from the formula of "operating current" times " operating factor". WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings. 61
MB90420G/5G (A) Series
2. Recommended Operating Conditions
Value Min. 4.5 Power supply voltage VCC AVCC DVCC Max. 5.5
(VSS = DVSS = AVSS = 0.0 V) Unit Remarks In normal operation: (MB90F428G/F428GA, MB90428G/428GA, MB90427G/427GA) Holding stop operation status (MB90F428G, MB90428G, MB90427G) Holding stop operation status (MB90F428GA, MB90428GA, MB90427GA) Use a ceramic capacitor or other capacitor of equivalent frequency characteristics. A smoothing capacitor on the VCC pin should have a capacitance greater than Cs.
Parameter
Symbol
V
3.0 4.5
5.5 5.5
V V
Smoothing capacitor* Operating temperature
CS
0.1
1.0
F
TA
-40
+105
C
* : For smoothing capacitor Cs connections, see the illustration below. * C pin connection
C
CS
VSS
DVSS
AVSS
WARNING: The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All of the device's electrical characteristics are warranted when the device is operated within these ranges. Always use semiconductor devices within their recommended operating condition ranges. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their FUJITSU representatives beforehand.
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MB90420G/5G (A) Series
3. DC Characteristics
Pin name
(VCC = 5.0 V10%, VSS = DVSS = AVSS = 0.0 V, TA = -40 C to +105 C) Conditions

Parameter "H"level input voltage "L"level input voltage
Symbol
Value Min. 0.8 VCC
VCC - 0.3 VSS - 0.3 VSS - 0.3
Typ. 45
Max.
VCC + 0.3 VCC + 0.3
Unit V V V V mA
Remarks CMOS hysteresis input pin*1 MD pin*2 CMOS hysteresis input pin*1 MD pin*2 MB90F428G/GA MB90F423G/GA
VIHS VIHM VILS VILM
0.6 VCC
VSS + 0.3
ICC
Operating frequency FCP = 16 MHz, normal operation

72
38
61
MB90428G/GA mA MB90427G/GA MB90423G/GA mA MB90F428G/GA MB90F423G/GA
ICCS
Operating frequency FCP = 16 MHz, sleep mode Operating frequency FCP = 2 MHz, time base timer mode Operating frequency FCP = 8 kHz, TA = 25 C, subclock operation Operating frequency FCP = 8 kHz, TA = 25 C, sub sleep operation Operating frequency FCP = 8 kHz, TA = 25 C, clock mode
15
24
13
21
MB90428G/GA, mA MB90427G/GA MB90423G/GA mA
Power supply current*3
ICTS
VCC
0.75
1.0
ICCL
0.35
0.7
mA
ICCLS
40
100
A
ICCT
40
100
A
*1 : All input pins except X0, X0A, MD0, MD1, MD2 pins. *2 : MD0, MD1, MD2 pins. *3 : Current values are provisional, and may be changed without prior notice for purposes of characteristic improve ment, etc. Supply current values assume external clock feed from the 1 pin and X1A pin. Users must be aware that supply current levels differ depending on whether an external clock or oscillator is useed. (Continued)
63
MB90420G/5G (A) Series
(Continued)
Sym bol (VCC = 5.0 V10%, VSS = DVSS = AVSS = 0.0 V, TA = -40 C to +105 C) Pin name Conditions Value Min. Typ. Max. Unit Remarks
Parameter
Power supply current *3 ICCH VCC TA = 25 C, stop mode
5
20
MB90F428G MB90F423G A MB90428G MB90427G MB90423G MB90F428GA MB90F423GA A MB90428GA MB90427GA MB90423GA A
40
100
Input leakage current
IIL
All input pins Other than Vcc, Vss, DVcc, DVss, Avcc, Avss, C, P70 to P77, P80 to P87 P70 to P77, P80 to P87 RST, MD0, MD1
VCC = DVCC = AVCC = 5.5 V VSS < VI < VCC
-5
5
Input capacitance 1
CIN1
5
15
pF
Input capacitance 2 Pull-up resistance Pull-down resistance Output H voltage 1 Output H voltage 2 Output L voltage 1 Output L voltage 2
CIN2 RUP
VCC = 4.5 V IOH = -4.0 mA VCC = 4.5 V IOH = -30.0 mA VCC = 4.5 V IOL = 4.0 mA VCC = 4.5 V IOL = 30.0 mA
25 25 VCC - 0.5 VCC - 0.5
15 50 50
45 100 100 0.4
pF k k
RDOWN MD2 Other than P70 to P77, P80 to P87 P70 to P77, P80 to P87 Other than P70 to P77, P80 to P87 P70 to P77, P80 to P87
VOH1
V
VOH2
V
VOL1
V
VOL2
0.5
V
*3: Current values are provisional, and may be changed without prior notice for purposes of characteristic improve ment, etc. Supply current values assume external clock feed from the 1 pin and X1A pin. Users must be aware that supply current levels differ depending on whether an external clock or oscillator is useed. (Continued)
64
MB90420G/5G (A) Series
(Continued)
Parameter Large current output drive capacity variation 1 Large current output drive capacity variation 2 LCD divider resistance COM0 to COM3 output impedance SEG0 to SEG3 output impedance
Symbol
Pin name PWM1Pn, PWM1Mn, PWM2Pn, PWM2Mn, n = 0 to 3 PWM1Pn, PWM1Mn, PWM2Pn, PWM2Mn, n = 0 to 3 V0 to V1, V1 to V2, V2 to V3 COMn (n = 0 to 3)
Conditions
Value Min. Typ. Max.
Unit
Remarks
VOH2
VCC = 4.5 V IOH = 30.0 mA VOH2 maximum variation
0
90
mV *4
VOL2
VCC = 4.5 V IOH = 30.0 mA VOL2 maximum variation
0
90
mV *4
RLCD
50
100
200
k
RVCOM
2.5
k
RVSEG
SEGn (n = 00 to 23) V0 to V3 COMm (m = 00 to 23) SEGn (n = 00 to 23)
15
k
LCD leakage current
ILCDC
-5.0
+5.0
k
*4 : Defined as maximum variation in VOH2/VOL2 with all channel 0 PWM1P0/PWM1M0/PWM2P0/PWM2M0 simultaneously ON. Similarly for other channels.
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MB90420G/5G (A) Series
4. AC Characteristics
(1) Clock timing Parameter Base oscillation clock frequency Base oscillation clock cycle time Input clock pulse width Input clock rise, fall time Input operating clock frequency Input operating clock cycle time Frequency variability ratio* (locked) Symbol FC FLC tCYL tLCYL PWH, PWL PWLH, PWLL tcr, tcf FCP FLCP tCP tLCP f (VCC = 5.0 V10%, VSS = DVSS = AVSS = 0.0 V, TA = -40 C to +105 C) Pin name X0, X1 X0A, X1A X0, X1 X0A, X1A X0 X0A X0, X0A Conditions Value Min. 10 2 62.5 Typ. 4 32.768 250 30.5 15.2 8.192 -- 122.1 Max. 5 16 500 5 Unit MHz kHz ns s ns s ns MHz With external clock signal Using main clock, PLL clock Using main clock, PLL clock Using sub clock Use duty ratio of 40 to 60% as a guideline Remarks
kHz Using sub clock ns s %
*: The frequency variability ratio is the maximum proportion of variation from the set central frequency using a multiplier in locked operation.
+ fo + x 100 (%)
f =
Central frequency
fo - -
* X0, X1 clock timing
t
X0
P tcf PLCYL tcr
0.8 VCC 0.2 VCC
* X0A, X1A clock timing
tHCYL
X0A
PWH tcf PWL tcr
0.8 VCC 0.2 VCC
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MB90420G/5G (A) Series
* Range of warranted operation
Relation between internal operating clock frequency and supply voltage MB90F428GA, MB90428GA, MB90427GA range of warranted operation 5.5
Supply voltage VCC (V)
3.7 3.3 3.0 PLL range of warranted operation MB90F428G, MB90428G, MB90427G range of warranted operation 2 8 12 16
Internal clock frequency fCP (MHz)
The MB90F428GA, MB90F423GA, MB90428GA, MB90427GA, and MB90423GA enter reset mode at supply voltage below 4 V 0.3 V. Relation between oscillator clock frequency and internal operating clock frequency Internal operating clock frequency PLL clock Main clock Multiplier x1 Oscillation clock frequency 4 MHz 2 MHz Multiplier x2 8 MHz Multiplier x3 12 MHz Multiplier x4 16 MHz
* Sample oscillator circuit Oscillator element Oscillator Frequency manufacturer TBD TBD 4 MHz
C1 TBD
C2 TBD
R TBD
X0
X1
R
C1
C2
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MB90420G/5G (A) Series
AC ratings are defined for the following measurement reference voltage values: * Input signal waveform Hysteresis input pin
0.8 VCC 0.6 VCC
* Output signal waveform Output pin
2.4 V 0.8 V
68
MB90420G/5G (A) Series
(2) Reset input
(VCC = 5.0 V10%, VSS = AVSS = 0.0 V, TA = -40 C to +105 C) Symbol tRSTL Pin name RST Conditions Value Min. 16 tCP Max. Unit ns Remarks
Parameter Reset input time
tRSTL
RST
0.6 VCC 0.6 VCC
(3) Power-on reset, power on conditions Pin Conditions name Value Min. 0.05 VCC 2.7 50
(VSS = 0.0 V, TA = -40 C to +105 C) Max. 30 0.2 Unit ms V V ms For repeat operation Remarks
Parameter Power supply rise time Power supply start voltage Power supply attained voltage Power supply cutoff time
Symbol
tR VOFF VON tOFF
tR
VCC
2.7 V 0.2 V 0.2 V tOFF 0.2 V
Extreme variations in voltage supply may activate a power-on reset. As the illustration below shows, when varying supply voltage during operation the use of a smooth voltage rise with suppressed fluctuation is recommended. Also in this situation, the PLL clock on the device should not be used, however it is permissible to use the PLL clock during a voltage drop of 1mV/s or less.
5.0 V
VCC
4.5 (V) 420G/425G series 3.0 (V) 420GA/425GA series
A rise slope of 50 mV or less is recommended RAM data hold
0V
VSS
69
MB90420G/5G (A) Series
(4) UART0, UART1 timing
(VCC = 5.0 V10%, VSS = AVSS = 0.0 V, TA = -40 C to +105 C)
Symbol
Parameter Serial clock cycle time SCK fall to SOT delay time Valid SIN to SCK rise SCK rise to valid SIN hold time Serial clock "H" pulse width Serial clock "L" pulse width SCK fall to SOT delay time Valid SIN to SCK rise SCK rise to valid SIN hold time
Pin name SCK0, SCK1 SCK0, SCK1 SOT0, SOT1 SCK0, SCK1 SIN0, SIN1 SCK0, SCK1 SCK0, SCK1 SOT0, SOT1 SCK0, SCK1 SIN0, SIN1
Conditions
Value Min. 8 tCP Max. 80 150
Unit ns ns ns ns ns ns ns ns ns
Remarks
tSCYC tSLOV tIVSH tSHIX tSHSL tSLSH tSLOV tIVSH tSHIX
-80 100 60 4 tCP 4 tCP
Internal shift clock mode output pin CL = 80 pF + 1*TTL
60 60
External shift clock mode output pin CL = 80 pF + 1*TTL
Notes : * AC ratings are for CLK synchronous mode. * CL is load capacitance connected to pin during testing. * Internal shift clock mode
SCK
0.8 V tSLOV 2.4 V tSCYC 2.4 V 0.8 V
SOT
0.8 V tIVSH 0.8 VCC tSHIX 0.8 VCC 0.6 VCC
SIN
0.6 VCC
* External shift clock mode
SCK
0.6 VCC tSLOV 2.4 V tSLSH 0.6 VCC tSHSL 0.8 VCC 0.8 VCC
SOT
0.8 V tIVSH 0.8 VCC tSHIX 0.8 VCC 0.6 VCC
SIN
0.6 VCC
70
MB90420G/5G (A) Series
(5) Timer input timing
(VCC = 5.0 V10%, VSS = AVSS = 0.0 V, TA = -40 C to +105 C) Symbol tTIWH tTIWL Pin name TIN0, TIN1, IN0, IN1, IN2, IN3, Conditions Value Min. 4 tCP Max. Unit Remarks
Parameter
Input pulse width
ns
* Timer input timing
tTIWH
tTIWL
TIN0 TIN1 IN0 IN3
0.8 VCC
0.8 VCC 0.6 VCC 0.6 VCC
(6) Trigger input timing
(VCC = 5.0 V10%, VSS = AVSS = 0.0 V, TA = -40 C to +105 C) Symbol tTRGL Pin name IRQ0 to IRQ7 Conditions Value Min. 5 tCP Max. Unit ns Remarks
Parameter Input pulse width
* Trigger input timing
tTRGH
tTRGL
IRQ0 IRQ7
0.8 VCC
0.8 VCC 0.6 VCC 0.6 VCC
71
MB90420G/5G (A) Series
(7) Low voltage detection
(VSS = AVSS = 0.0 V, TA = -40 C to +105 C) Value Min. 3.7 0.1 -0.1 Typ. 4.0 Max. 4.3 0.02 35 Unit V V V/s s Remarks During voltage drop During voltage rise
Parameter Detection voltage Hysteresis width Power supply voltage fluctuation ratio Detection delay time
Symbol Pin name Conditions
VDL VHYS dV/dt td
VCC VCC VCC
Internal reset
VCC
dV dt Vni VHYS
td
td
72
MB90420G/5G (A) Series
5. A/D Conversion Block
(1) Electrical Characteristics (VCC = AVCC = 5.0 V10%, VSS = AVSS = 0.0 V, TA = -40 C to +105 C) Pin name AN0 to AN7 AN0 to AN7 AN0 to AN7 AN0 to AN7 AVRH AVCC AVRH AVRH AN0 to AN7 Value Min. Typ. Max. 10 5.0 2.5 1.9 Unit bit LSB LSB LSB V V s s s A V V mA A A A LSB *4 VAVRH = 5.0 V *4 1 LSB = (AVRH - AVSS) / 1024 *1 *2 *3 VAVSS = VAIN = VAVCC Remarks
Parameter Resolution Total error Non-linear error Differential linear error Zero transition voltage Full scale transition voltage Sampling time Compare time A/D conversion time Analog port input current Analog input current Reference voltage Power supply current Reference voltage feed current Inter-channel variation
Symbol VOT VFST tSMP tCMP tCNV IAIN VAIN AVR+ IA IAH IR IRH --
AVSS AVSS AVSS - 3.5 LSB + 0.5 LSB + 4.5 LSB AVRH AVRH AVRH - 6.5 LSB - 1.5 LSB + 1.5 LSB 2.000 4.125 6.125 0 3.0 200 2.3 400 10 AVRH AVCC 6.0 5 600 5 4
*1 : At FCP = 16 MHz, tSMP = 32 x tCP = 2.000 (s) . *2 : At FCP = 16 MHz, tCMP = 66 x tCP = 4.125 (s) . . *3 : Equivalent to conversion time per channel at FCP = 16 MHz, and selection of tSMP = 32 x tCP and tCMP = 32 x tCP *4 : Defined as supply current (when VCC = AVCC = AVRH = 5.0 V) with A/D converter not operating, and CPU in stop mode. Notes : *The relative error increases as AVRH is reduced. *The output impedance (rs) on the external analog input circuit should be used as follows. External circuit output impedance rs = 5 k max. *If the output impedance on the external circuit is too great, the analog voltage sampling time may be insufficient. *If DC inhibitor capacitance is placed between the external circuit and input pin, then a capacitance value several thousand times the value of the chip internal sampling capacitance (CSH) should be selected in order to suppress the effects of voltage division with CSH.
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MB90420G/5G (A) Series
* Analog input equivalent circuit
Microcontroller internal circuits
Input pin AN0 rS RSH
CSH Comparator
Input pin AN7 VS External circuits Analog channel selector S/H circuit
rs = 5 k or less RSH = approx. 3 k CSH = approx. 25 pF Note : These element parameters are intended as guidelines for reference, and are not warranted for actual use.
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MB90420G/5G (A) Series
(2) Definition of terms * Resolution Indicates the ability of the A/D converter to discriminate in analog conversion. 10-bit resolution indicates that analog voltage can be resolved into 210 = 1024 levels. * Total error Expresses the difference between actual and logical values. It is the total value of errors that can come from offset error, gain error, non-linearity error and noise. * Linearity error Expresses the deviation between actual conversion characteristics and a straight line connecting the device's zero transition point (00 0000 0000 00 0000 0001) and full scale transition point (11 1111 1110 11 1111 1111) . * Differential linearity error Expresses the deviation of the logical value of input voltage required to create a variation of 1 SLB in output code. * 10-bit A/D converter conversion characteristics
11 11 11 11
1111 1111 1111 1111 . . . . .
1111 1110 1101 1100
1 LSB x N + VOT
Digital output
. . . . . . . . 00 0000 0011 00 0000 0010 00 0000 0001 00 0000 0000 VOT VNT V(N + 1)T Analog input 1 LSB = VFST - VOT 1022 Linearity error = Differential linearity error = VNT - (1 LSB x N + VOT) [LSB] 1 LSB V (N + 1) T - VNT - 1 [LSB] 1 LSB VFST Linearity error
75
MB90420G/5G (A) Series
s EXAMPLE CHARACTERISTICS
ICC - VCC (TA = +25 C)
40 35 30 ICC (mA) 25 20 15 10 5 0 3.5 4.5 VCC (V) 5.5 FC = 11 MHz FC = 8 MHz FC = 5 MHz FC = 4 MHz FC = 2 MHz 6.5 FC = 16 MHz
ICCS - VCC (TA = +25 C)
3.5 3 2.5 ICCS (mA) 2 1.5 1 0.5 0 3.5 4.5 VCC (V) 5.5 6.5 FC = 11 MHz FC = 8 MHz FC = 5 MHz FC = 4 MHz FC = 2 MHz FC = 16 MHz
ICTS - VCC (TA = +25 C)
900 800 700 ICTS (A) 600 500 400 300 200 100 0 3.5 4.5 VCC (V) 5.5 6.5 FC = 16 MHz FC = 11 MHz FC = 8 MHz FC = 5 MHz FC = 4 MHz FC = 2 MHz
(Continued)
76
MB90420G/5G (A) Series
(Continued)
ICCL - VCC (FC = 8 kHz)
500 400 ICCL (A) 300 200 100 0 3.5 4.5 VCC (V) 5.5 6.5 Ta = -40 C
Ta = 25 C Ta = 125 C
ICCLS - VCC (FC = 8 kHz)
70 60 50 ICCLS (A) 40 30 20 10 0 3.5 4.5 VCC (V) 5.5 6.5 Ta = -40 C Ta = 25 C Ta = 125 C
ICCT - VCC (FC = 8 kHz)
70 60 50 ICCT (A) 40 30 20 10 0 3.5 4.5 VCC (V) 5.5 6.5 Ta = -40 C Ta = 25 C Ta = 125 C
77
MB90420G/5G (A) Series
s INSTRUCTIONS (351 INSTRUCTIONS)
Table 1 Item Mnemonic # ~ Explanation of Items in Tables of Instructions Meaning Upper-case letters and symbols: Represented as they appear in assembler. Lower-case letters: Replaced when described in assembler. Numbers after lower-case letters: Indicate the bit width within the instruction code. Indicates the number of bytes. Indicates the number of cycles. m : When branching n : When not branching See Table 4 for details about meanings of other letters in items. Indicates the number of accesses to the register during execution of the instruction. It is used calculate a correction value for intermittent operation of CPU. Indicates the correction value for calculating the number of actual cycles during execution of the instruction. (Table 5) The number of actual cycles during execution of the instruction is the correction value summed with the value in the "~" column. Indicates the operation of instruction. Indicates special operations involving the upper 8 bits of the lower 16 bits of the accumulator. Z : Transfers "0". X : Extends with a sign before transferring. - : Transfers nothing. Indicates special operations involving the upper 16 bits in the accumulator. * : Transfers from AL to AH. - : No transfer. Z : Transfers 00H to AH. X : Transfers 00H or FFH to AH by signing and extending AL. Indicates the status of each of the following flags: I (interrupt enable), S (stack), T (sticky bit), N (negative), Z (zero), V (overflow), and C (carry). * : Changes due to execution of instruction. - : No change. S : Set by execution of instruction. R : Reset by execution of instruction.
RG B
Operation LH
AH
I S T N Z V C
RMW
Indicates whether the instruction is a read-modify-write instruction. (a single instruction that reads data from memory, etc., processes the data, and then writes the result to memory.) * : Instruction is a read-modify-write instruction. - : Instruction is not a read-modify-write instruction. Note: A read-modify-write instruction cannot be used on addresses that have different meanings depending on whether they are read or written.
* Number of execution cycles The number of cycles required for instruction execution is acquired by adding the number of cycles for each instruction, a corrective value depending on the condition, and the number of cycles required for program fetch. Whenever the instruction being executed exceeds the two-byte (word) boundary, a program on an internal ROM connected to a 16-bit bus is fetched. If data access is interfered with, therefore, the number of execution cycles is increased. For each byte of the instruction being executed, a program on a memory connected to an 8-bit external data bus is fetched. If data access in interfered with, therefore, the number of execution cycles is increased. When a general-purpose register, an internal ROM, an internal RAM, an internal I/O device, or an external bus is accessed during intermittent CPU operation, the CPU clock is suspended by the number of cycles specified by the CG1/0 bit of the low-power consumption mode control register. When determining the number of cycles required for instruction execution during intermittent CPU operation, therefore, add the value of the number of times access is done x the number of cycles suspended as the corrective value to the number of ordinary execution cycles.
78
MB90420G/5G (A) Series
Table 2 Symbol A Explanation of Symbols in Tables of Instructions Meaning 32-bit accumulator The bit length varies according to the instruction. Byte : Lower 8 bits of AL Word : 16 bits of AL Long : 32 bits of AL and AH Upper 16 bits of A Lower 16 bits of A Stack pointer (USP or SSP) Program counter Program bank register Data bank register Additional data bank register System stack bank register User stack bank register Current stack bank register (SSB or USB) Direct page register DTB, ADB, SSB, USB, DPR, PCB, SPB DTB, ADB, SSB, USB, DPR, SPB R0, R1, R2, R3, R4, R5, R6, R7 RW0, RW1, RW2, RW3, RW4, RW5, RW6, RW7 RW0, RW1, RW2, RW3 RL0, RL1, RL2, RL3 Compact direct addressing Direct addressing Physical direct addressing Bit 0 to bit 15 of addr24 Bit 16 to bit 23 of addr24 I/O area (000000H to 0000FFH) 4-bit immediate data 8-bit immediate data 16-bit immediate data 32-bit immediate data 16-bit data signed and extended from 8-bit immediate data 8-bit displacement 16-bit displacement Bit offset Vector number (0 to 15) Vector number (0 to 255) Bit address PC relative addressing Effective addressing (codes 00 to 07) Effective addressing (codes 08 to 1F) Register list
AH AL SP PC PCB DTB ADB SSB USB SPB DPR brg1 brg2 Ri RWi RWj RLi dir addr16 addr24 ad24 0 to 15 ad24 16 to 23 io imm4 imm8 imm16 imm32 ext (imm8) disp8 disp16 bp vct4 vct8 ( )b rel ear eam rlst
79
MB90420G/5G (A) Series
Table 3 Code 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F R0 R1 R2 R3 R4 R5 R6 R7 Notation RW0 RW1 RW2 RW3 RW4 RW5 RW6 RW7 RL0 (RL0) RL1 (RL1) RL2 (RL2) RL3 (RL3) Effective Address Fields Address format Register direct "ea" corresponds to byte, word, and long-word types, starting from the left Number of bytes in address extension *
--
@RW0 @RW1 @RW2 @RW3 @RW0 + @RW1 + @RW2 + @RW3 + @RW0 + disp8 @RW1 + disp8 @RW2 + disp8 @RW3 + disp8 @RW4 + disp8 @RW5 + disp8 @RW6 + disp8 @RW7 + disp8 @RW0 + disp16 @RW1 + disp16 @RW2 + disp16 @RW3 + disp16 @RW0 + RW7 @RW1 + RW7 @PC + disp16 addr16
Register indirect 0 Register indirect with post-increment 0 Register indirect with 8-bit displacement 1
Register indirect with 16-bit displacement
2 0 0 2 2
Register indirect with index Register indirect with index PC indirect with 16-bit displacement Direct address
Note : The number of bytes in the address extension is indicated by the "+" symbol in the "#" (number of bytes) column in the tables of instructions.
80
MB90420G/5G (A) Series
Table 4 Code Number of Execution Cycles for Each Type of Addressing (a) Operand Ri RWi RLi @RWj @RWj + @RWi + disp8 @RWj + disp16 @RW0 + RW7 @RW1 + RW7 @PC + disp16 addr16 Number of execution cycles for each type of addressing Listed in tables of instructions 2 4 2 2 4 4 2 1 Number of register accesses for each type of addressing
00 to 07 08 to 0B 0C to 0F 10 to 17 18 to 1B 1C 1D 1E 1F
Listed in tables of instructions 1 2 1 1 2 2 0 0
Note : "(a)" is used in the "~" (number of states) column and column B (correction value) in the tables of instructions. Table 5 Compensation Values for Number of Cycles Used to Calculate Number of Actual Cycles Operand Internal register Internal memory even address Internal memory odd address Even address on external data bus (16 bits) Odd address on external data bus (16 bits) External data bus (8 bits) (b) byte
Cycles Access
(c) word
Cycles Access
(d) long
Cycles Access
+0 +0 +0 +1 +1 +1
1 1 1 1 1 1
+0 +0 +2 +1 +4 +4
1 1 2 1 2 2
+0 +0 +4 +2 +8 +8
2 2 4 2 4 4
Notes: * "(b)", "(c)", and "(d)" are used in the "~" (number of states) column and column B (correction value) in the tables of instructions. * When the external data bus is used, it is necessary to add in the number of wait cycles used for ready input and automatic ready. Table 6 Correction Values for Number of Cycles Used to Calculate Number of Program Fetch Cycles Instruction Internal memory External data bus (16 bits) External data bus (8 bits) Byte boundary -- -- +3 Word boundary +2 +3 --
Notes: * When the external data bus is used, it is necessary to add in the number of wait cycles used for ready input and automatic ready. * Because instruction execution is not slowed down by all program fetches in actuality, these correction values should be used for "worst case" calculations.
81
MB90420G/5G (A) Series
Table 7 Mnemonic MOV MOV MOV MOV MOV MOV MOV MOV MOV MOVN MOVX MOVX MOVX MOVX MOVX MOVX MOVX MOVX MOVX MOVX MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV /MOV XCH XCH XCH XCH A, dir A, addr16 A, Ri A, ear A, eam A, io A, #imm8 A, @A A, @RLi+disp8 A, #imm4 A, dir A, addr16 A, Ri A, ear A, eam A, io A, #imm8 A, @A A,@RWi+disp8 A, @RLi+disp8 dir, A addr16, A Ri, A ear, A eam, A io, A @RLi+disp8, A Ri, ear Ri, eam ear, Ri eam, Ri Ri, #imm8 io, #imm8 dir, #imm8 ear, #imm8 eam, #imm8 @AL, AH @A, T A, ear A, eam Ri, ear Ri, eam # ~ Transfer Instructions (Byte) [41 Instructions]
RG
B (b) (b) 0 0 (b) (b) 0 (b) (b) 0 (b) (b) 0 0 (b) (b) 0 (b) (b) (b) (b) (b) 0 0 (b) (b) (b) 0 (b) 0 (b) 0 (b) (b) 0 (b) (b) 0 2x (b) 0 2x (b)
Operation byte (A) (dir) byte (A) (addr16) byte (A) (Ri) byte (A) (ear) byte (A) (eam) byte (A) (io) byte (A) imm8 byte (A) ((A)) byte (A) ((RLi)+disp8) byte (A) imm4 byte (A) (dir) byte (A) (addr16) byte (A) (Ri) byte (A) (ear) byte (A) (eam) byte (A) (io) byte (A) imm8 byte (A) ((A)) byte (A) ((RWi)+disp8) byte (A) ((RLi)+disp8) byte (dir) (A) byte (addr16) (A) byte (Ri) (A) byte (ear) (A) byte (eam) (A) byte (io) (A) byte ((RLi) +disp8) (A) byte (Ri) (ear) byte (Ri) (eam) byte (ear) (Ri) byte (eam) (Ri) byte (Ri) imm8 byte (io) imm8 byte (dir) imm8 byte (ear) imm8 byte (eam) imm8 byte ((A)) (AH) byte (A) (ear) byte (A) (eam) byte (Ri) (ear) byte (Ri) (eam)
LH AH
I
S
T
N
Z
V
C
RMW
3 2 4 3 2 1 2 2 2+ 3+ (a) 3 2 2 2 3 2 10 3 1 1 3 2 4 3 2 2 2 2 2+ 3+ (a) 3 2 2 2 3 2 5 2 10 3 2 3 1 2 2+ 2 3 2 2+ 2 2+ 2 3 3 3 3+ 2 3 4 2 2 3+ (a) 3 10 3 4+ (a) 4 5+ (a) 2 5 5 2 4+ (a) 3
0 0 1 1 0 0 0 0 2 0 0 0 1 1 0 0 0 0 1 2 0 0 1 1 0 0 2 2 1 2 1 1 0 0 1 0 0 2 0 4 2
Z Z Z Z Z Z Z Z Z Z
* * * * * * * - * *
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
-* -* -* -* -* -* -* -* -* -R - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - * * * * * * * * * * * * * * * * * * * * * * - - * - * - - - -
* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * - - * - * - - - -
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
X* X* X* X* X* X* X* X- X* X* - - - - - - - - - - - - - - - - - Z Z - - - - - - - - - - - - - - - - - - - - - - -
4 2 2+ 5+ (a) 7 2 2+ 9+ (a)
Note : For an explanation of "(a)" to "(d)", refer to Table 4, "Number of Execution Cycles for Each Type of Addressing," and Table 5, "Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles."
82
MB90420G/5G (A) Series
Table 8 Mnemonic MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW A, dir A, addr16 A, SP A, RWi A, ear A, eam A, io A, @A A, #imm16 A, @RWi+disp8 A, @RLi+disp8 # Transfer Instructions (Word/Long Word) [38 Instructions] ~
RG
B (c) (c) 0 0 0 (c) (c) (c) 0 (c) (c) (c) (c) 0 0 0 (c) (c) (c) (c) (0) (c) 0 (c) 0 (c) 0 (c) (c)
Operation word (A) (dir) word (A) (addr16) word (A) (SP) word (A) (RWi) word (A) (ear) word (A) (eam) word (A) (io) word (A) ((A)) word (A) imm16
LH AH
I
S
T
N
Z
V
C
RMW
2 3 3 4 1 1 1 2 2 2 2+ 3+ (a) 2 3 2 3 3 2 2 5 3 10 2 3 1 1 2 2+ 2 2 3 2 2+ 2 2+ 3 4 4 4+ 2 3 4 1 2 2 3+ (a) 3 5 10 3 4+ (a) 4 5+ (a) 2 5 2 4+ (a) 3
0 0 0 1 1 0 0 0 0 1 2 0 0 0 1 1 0 0 1 2 2 1 2 1 1 0 1 0 0
- - - - - - - - - word (A) ((RWi) +disp8) - word (A) ((RLi) +disp8) - word (dir) (A) word (addr16) (A) word (SP) (A) word (RWi) (A) word (ear) (A) word (eam) (A) word (io) (A) - - - - - - - word ((RWi) +disp8) (A) - word ((RLi) +disp8) (A) - word (RWi) (ear) - word (RWi) (eam) - word (ear) (RWi) - word (eam) (RWi) - word (RWi) imm16 - word (io) imm16 - word (ear) imm16 - word (eam) imm16 - word ((A)) (AH) word (A) (ear) word (A) (eam) word (RWi) (ear) word (RWi) (eam) long (A) (ear) long (A) (eam) long (A) imm32 long (ear) (A) long (eam) (A) - - - - - - - - - -
* * * * * * * - * * * - - - - - - - - - - - - - - - - - - - - - - - - - - -
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
* * * * * * * * * * * * * * * * * * * * * * * * * - * - * - - - - * * * * *
* * * * * * * * * * * * * * * * * * * * * * * * * - * - * - - - - * * * * *
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
MOVW dir, A MOVW addr16, A MOVW SP A , MOVW RWi, A MOVW ear, A MOVW eam, A MOVW io, A MOVW @RWi+disp8, A MOVW @RLi+disp8, A MOVW RWi, ear MOVW RWi, eam MOVW ear, RWi MOVW eam, RWi MOVW RWi, #imm16 MOVW io, #imm16 MOVW ear, #imm16 MOVW eam, #imm16 MOVW @AL, AH /MOVW@A, T XCHW XCHW XCHW XCHW A, ear A, eam RWi, ear RWi, eam
2 4 2+ 5+ (a) 2 7 2+ 9+ (a) 2 4 2+ 5+ (a) 5 3 2 4 2+ 5+ (a)
2 0 0 2x (c) 4 0 2 2x (c) 2 0 0 2 0 0 (d) 0 0 (d)
MOVL A, ear MOVL A, eam MOVL A, #imm32 MOVL ear, A MOVL eam, A
Note : For an explanation of "(a)" to "(d)", refer to Table 4, "Number of Execution Cycles for Each Type of Addressing," and Table 5, "Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles."
83
MB90420G/5G (A) Series
Table 9 Mnemonic ADD ADD ADD ADD ADD ADD ADDC ADDC ADDC ADDDC SUB SUB SUB SUB SUB SUB SUBC SUBC SUBC SUBDC A,#imm8 A, dir A, ear A, eam ear, A eam, A A A, ear A, eam A A, #imm8 A, dir A, ear A, eam ear, A eam, A A A, ear A, eam A Addition and Subtraction Instructions (Byte/Word/Long Word) [42 Instructions] # 2 2 2 2+ 2 2+ 1 2 2+ 1 2 2 2 2+ 2 2+ 1 2 2+ 1 1 2 2+ 3 2 2+ 2 2+ 1 2 2+ 3 2 2+ 2 2+ ~ 2 5 3 4+ (a) 3 5+ (a) 2 3 4+ (a) 3 2 5 3 4+ (a) 3 5+ (a) 2 3 4+ (a) 3 2 3 4+ (a) 2 3 5+ (a) 3 4+ (a) 2 3 4+ (a) 2 3 5+ (a) 3 4+ (a)
RG
B 0 (b) 0 (b) 0 2x (b) 0 0 (b) 0 0 (b) 0 (b) 0 2x (b) 0 0 (b) 0 0 0 (c) 0 0 2x (c) 0 (c) 0 0 (c) 0 0 2x (c) 0 (c) 0 (d) 0 0 (d) 0
Operation byte (A) (A) +imm8 byte (A) (A) +(dir) byte (A) (A) +(ear) byte (A) (A) +(eam) byte (ear) (ear) + (A) byte (eam) (eam) + (A) byte (A) (AH) + (AL) + (C) byte (A) (A) + (ear) + (C) byte (A) (A) + (eam) + (C)
LH AH
I
S
T
N
Z
V
C
RMW
0 0 1 0 2 0 0 1 0 0 0 0 1 0 2 0 0 1 0 0 0 1 0 0 2 0 1 0 0 1 0 0 2 0 1 0 2 0 0 2 0 0
Z Z Z Z - Z Z Z Z byte (A) (AH) + (AL) + (C) (decimal) Z Z byte (A) (A) -imm8 Z byte (A) (A) - (dir) Z byte (A) (A) - (ear) Z byte (A) (A) - (eam) - byte (ear) (ear) - (A) - byte (eam) (eam) - (A) byte (A) (AH) - (AL) - (C) Z byte (A) (A) - (ear) - (C) Z byte (A) (A) - (eam) - (C) Z byte (A) (AH) - (AL) - (C) (decimal) Z word (A) (AH) + (AL) word (A) (A) +(ear) word (A) (A) +(eam) word (A) (A) +imm16 word (ear) (ear) + (A) word (eam) (eam) + (A) word (A) (A) + (ear) + (C) word (A) (A) + (eam) + (C) word (A) (AH) - (AL) word (A) (A) - (ear) word (A) (A) - (eam) word (A) (A) -imm16 word (ear) (ear) - (A) word (eam) (eam) - (A) word (A) (A) - (ear) - (C) word (A) (A) - (eam) - (C) long (A) (A) + (ear) long (A) (A) + (eam) long (A) (A) +imm32 long (A) (A) - (ear) long (A) (A) - (eam) long (A) (A) -imm32 - - - - - - - - - - - - - - - - - - - - - -
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
- - - - - * - - - - - - - - - * - - - - - - - - - * - - - - - - - * - - - - - - - -
ADDW A ADDW A, ear ADDW A, eam ADDW A, #imm16 ADDW ear, A ADDW eam, A ADDCW A, ear ADDCW A, eam SUBW A SUBW A, ear SUBW A, eam SUBW A, #imm16 SUBW ear, A SUBW eam, A SUBCW A, ear SUBCW A, eam ADDL ADDL ADDL SUBL SUBL SUBL
A, ear 2 6 A, eam 2+ 7+ (a) A, #imm32 5 4 A, ear 2 6 A, eam 2+ 7+ (a) A, #imm32 5 4
Note : For an explanation of "(a)" to "(d)", refer to Table 4, "Number of Execution Cycles for Each Type of Addressing," and Table 5, "Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles."
84
MB90420G/5G (A) Series
Table 10 Mnemonic INC INC DEC DEC INCW INCW ear eam ear eam ear eam Increment and Decrement Instructions (Byte/Word/Long Word) [12 Instructions] # ~
RG
B
Operation
LH
AH
I
S
T
N
Z
V
C
RMW
2 2 2+ 5+ (a) 2 3 2+ 5+ (a) 2 3 2+ 5+ (a) 2 3 2+ 5+ (a) 2 7 2+ 9+ (a) 2 7 2+ 9+ (a)
2 0 2 0 2 0 2 0 4 0 4 0
0 byte (ear) (ear) +1 2x (b) byte (eam) (eam) +1 0 byte (ear) (ear) -1 2x (b) byte (eam) (eam) -1 0 word (ear) (ear) +1 2x (c) word (eam) (eam) +1 0 word (ear) (ear) -1 2x (c) word (eam) (eam) -1 0 long (ear) (ear) +1 2x (d) long (eam) (eam) +1 0 long (ear) (ear) -1 2x (d) long (eam) (eam) -1
- - - - - - - - - - - -
- - - - - - - - - - - -
- - - - - - - - - - - -
- - - - - - - - - - - -
- - - - - - - - - - - -
* * * * * * * * * * * *
* * * * * * * * * * * *
* * * * * * * * * * * *
- - - - - - - - - - - -
- * - * - * - * - * - *
DECW ear DECW eam INCL INCL DECL DECL ear eam ear eam
Note : For an explanation of "(a)" to "(d)", refer to Table 4, "Number of Execution Cycles for Each Type of Addressing," and Table 5, "Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles." Table 11 Mnemonic CMP CMP CMP CMP CMPW CMPW CMPW CMPW CMPL CMPL CMPL A A, ear A, eam A, #imm8 # 1 2 2+ 2 Compare Instructions (Byte/Word/Long Word) [11 Instructions] ~ 1 2 3+ (a) 2 1 2 3+ (a) 2 6 7+ (a) 3
RG
B 0 0 (b) 0 0 0 (c) 0 0 (d) 0
Operation byte (AH) - (AL) byte (A) (ear) byte (A) (eam) byte (A) imm8 word (AH) - (AL) word (A) (ear) word (A) (eam) word (A) imm16 word (A) (ear) word (A) (eam) word (A) imm32
LH
AH
I
S
T
N
Z
V
C
RMW
0 1 0 0 0 1 0 0 2 0 0
- - - - - - - - - - -
- - - - - - - - - - -
- - - - - - - - - - -
- - - - - - - - - - -
- - - - - - - - - - -
* * * * * * * * * * *
* * * * * * * * * * *
* * * * * * * * * * *
* * * * * * * * * * *
- - - - - - - - - - -
A 1 A, ear 2 A, eam 2+ A, #imm16 3 A, ear 2 A, eam 2+ A, #imm32 5
Note : For an explanation of "(a)" to "(d)", refer to Table 4, "Number of Execution Cycles for Each Type of Addressing," and Table 5, "Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles."
85
MB90420G/5G (A) Series
Table 12 Mnemonic DIVU DIVU DIVU A A, ear Multiplication and Division Instructions (Byte/Word/Long Word) [11 Instructions] # 1 2 ~ *
1
RG
B
Operation
Quotient byte (AL) Remainder byte (AH) Quotient byte (A) Remainder byte (ear) Quotient byte (A) Remainder byte (eam) Quotient word (A) Remainder word (ear) Quotient word (A) Remainder word (eam)
LH AH
I
S
T
N
Z
V
C
RMW
0 1 0 1 0
0 word (AH) /byte (AL) 0 word (A)/byte (ear)
- - - - - - - - - - -
- - - - - - - - - - -
- - - - - - - - - - -
- - - - - - - - - - -
- - - - - - - - - - -
- - - - - - - - - - -
- - - - - - - - - - -
* * * * * - - - - - -
* * * * * - - - - - -
- - - - - - - - - - -
*2
A, eam 2+ *3 2 *4
*6 word (A)/byte (eam) 0 long (A)/word (ear)
DIVUW A, ear
DIVUW A, eam 2+ *5 MULU MULU MULU A 1 *8 A, ear 2 *9 A, eam 2+ *10
*7 long (A)/word (eam)
0 0 byte (AH) *byte (AL) word (A) 1 0 byte (A) *byte (ear) word (A) 0 (b) byte (A) *byte (eam) word (A) 0 0 word (AH) *word (AL) long (A) 1 0 word (A) *word (ear) long (A) 0 (c) word (A) *word (eam) long (A)
MULUW A 1 *11 MULUW A, ear 2 *12 MULUW A, eam 2+ *13 *1: *2: *3: *4: *5: *6: *7: *8: *9: *10: *11: *12: *13:
3 when the result is zero, 7 when an overflow occurs, and 15 normally. 4 when the result is zero, 8 when an overflow occurs, and 16 normally. 6 + (a) when the result is zero, 9 + (a) when an overflow occurs, and 19 + (a) normally. 4 when the result is zero, 7 when an overflow occurs, and 22 normally. 6 + (a) when the result is zero, 8 + (a) when an overflow occurs, and 26 + (a) normally. (b) when the result is zero or when an overflow occurs, and 2 x (b) normally. (c) when the result is zero or when an overflow occurs, and 2 x (c) normally. 3 when byte (AH) is zero, and 7 when byte (AH) is not zero. 4 when byte (ear) is zero, and 8 when byte (ear) is not zero. 5 + (a) when byte (eam) is zero, and 9 + (a) when byte (eam) is not 0. 3 when word (AH) is zero, and 11 when word (AH) is not zero. 4 when word (ear) is zero, and 12 when word (ear) is not zero. 5 + (a) when word (eam) is zero, and 13 + (a) when word (eam) is not zero.
Note : For an explanation of "(a)" to "(d)", refer to Table 4, "Number of Execution Cycles for Each Type of Addressing," and Table 5, "Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles."
86
MB90420G/5G (A) Series
Table 13 Signed Multiplication and Division Instructions (Byte/Word/Long Word) [11 Instructions] # 2 2 ~ *1 *2 *3 *4 *5
RG
Mnemonic DIV DIV DIV DIVW DIVW A A, ear
B 0
Operation
LH
AH
I
S
T
N
Z
V
C
RMW
0 1 0 1 0
A, eam 2 + A, ear A, eam 2 2+
word (AH) /byte (AL) Quotient byte (AL) Remainder byte (AH) 0 word (A)/byte (ear) Quotient byte (A) Remainder byte (ear) *6 word (A)/byte (eam) Quotient byte (A) Remainder byte (eam) 0 long (A)/word (ear) Quotient word (A) Remainder word (ear) *7 long (A)/word (eam) Quotient word (A) Remainder word (eam) 0 0 (b) 0 0 (c) byte (AH) *byte (AL) word (A) byte (A) *byte (ear) word (A) byte (A) *byte (eam) word (A) word (AH) *word (AL) long (A) word (A) *word (ear) long (A) word (A) *word (eam) long (A)
Z Z Z - -
- - - - -
- - - - -
- - - - -
- - - - -
- - - - -
- - - - -
* * * * *
* * * * *
- - - - -
MULU MULU MULU MULUW MULUW MULUW *1: *2: *3: *4:
A 2 A, ear 2 A, eam 2 + A 2 A, ear 2 A, eam 2 +
*8 *9 *10 *11 *12 *13
0 1 0 0 1 0
- - - - - -
- - - - - -
- - - - - -
- - - - - -
- - - - - -
- - - - - -
- - - - - -
- - - - - -
- - - - - -
- - - - - -
Set to 3 when the division-by-0, 8 or 18 for an overflow, and 18 for normal operation. Set to 3 when the division-by-0, 10 or 21 for an overflow, and 22 for normal operation. Set to 4 + (a) when the division-by-0, 11 + (a) or 22 + (a) for an overflow, and 23 + (a) for normal operation. Positive dividend: Set to 4 when the division-by-0, 10 or 29 for an overflow, and 30 for normal operation. Negative dividend: Set to 4 when the division-by-0, 11 or 30 for an overflow and 31 for normal operation. *5: Positive dividend: Set to 4 + (a) when the division-by-0, 11 + (a) or 30 + (a) for an overflow, and 31 + (a) for normal operation. Negative dividend: Set to 4 + (a) when the division-by-0, 12 + (a) or 31 + (a) for an overflow, and 32 + (a) for normal operation. *6: When the division-by-0, (b) for an overflow, and 2 x (b) for normal operation. *7: When the division-by-0, (c) for an overflow, and 2 x (c) for normal operation. *8: Set to 3 when byte (AH) is zero, 12 when the result is positive, and 13 when the result is negative. *9: Set to 3 when byte (ear) is zero, 12 when the result is positive, and 13 when the result is negative. *10: Set to 4 + (a) when byte (eam) is zero, 13 + (a) when the result is positive, and 14 + (a) when the result is negative. *11: Set to 3 when word (AH) is zero, 12 when the result is positive, and 13 when the result is negative. *12: Set to 3 when word (ear) is zero, 16 when the result is positive, and 19 when the result is negative. *13: Set to 4 + (a) when word (eam) is zero, 17 + (a) when the result is positive, and 20 + (a) when the result is negative. Notes: * When overflow occurs during DIV or DIVW instruction execution, the number of execution cycles takes two values because of detection before and after an operation. * When overflow occurs during DIV or DIVW instruction execution, the contents of AL are destroyed. * For (a) to (d), refer to "Table 4 Number of Execution Cycles for Effective Address in Addressing Modes" and "Table 5 Correction Values for Number of Cycles for Calculating Actual Number of Cycles."
87
MB90420G/5G (A) Series
Table 14 Mnemonic AND AND AND AND AND OR OR OR OR OR XOR XOR XOR XOR XOR NOT NOT NOT ANDW ANDW ANDW ANDW ANDW ANDW ORW ORW ORW ORW ORW ORW XORW XORW XORW XORW XORW XORW A, #imm8 A, ear A, eam ear, A eam, A A, #imm8 A, ear A, eam ear, A eam, A A, #imm8 A, ear A, eam ear, A eam, A A ear eam # ~ Logical 1 Instructions (Byte/Word) [39 Instructions]
RG
B 0 0 (b) 0 2x (b) 0 0 (b) 0 2x (b) 0 0 (b) 0 2x (b)
Operation byte (A) (A) and imm8 byte (A) (A) and (ear) byte (A) (A) and (eam) byte (ear) (ear) and (A) byte (eam) (eam) and (A) byte (A) (A) or imm8 byte (A) (A) or (ear) byte (A) (A) or (eam) byte (ear) (ear) or (A) byte (eam) (eam) or (A) byte (A) (A) xor imm8 byte (A) (A) xor (ear) byte (A) (A) xor (eam) byte (ear) (ear) xor (A) byte (eam) (eam) xor (A)
LH AH
I
S
T
N
Z
V
C
RMW
2 2 2 3 2+ 4+ (a) 2 3 2+ 5+ (a) 2 2 2 3 2+ 4+ (a) 2 3 2+ 5+ (a) 2 2 2 3 2+ 4+ (a) 2 3 2+ 5+ (a) 1 2 2 3 2+ 5+ (a)
0 1 0 2 0 0 1 0 2 0 0 1 0 2 0 0 2 0 0 0 1 0 2 0 0 0 1 0 2 0 0 0 1 0 2 0 0 2 0
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
- - - - * - - - - * - - - - * - - * - - - - - * - - - - - * - - - - - * - - *
0 byte (A) not (A) 0 byte (ear) not (ear) 2x (b) byte (eam) not (eam) 0 0 0 (c) 0 2x (c) 0 0 0 (c) 0 2x (c) 0 0 0 (c) 0 2x (c) word (A) (AH) and (A) word (A) (A) and imm16 word (A) (A) and (ear) word (A) (A) and (eam) word (ear) (ear) and (A) word (eam) (eam) and (A) word (A) (AH) or (A) word (A) (A) or imm16 word (A) (A) or (ear) word (A) (A) or (eam) word (ear) (ear) or (A) word (eam) (eam) or (A) word (A) (AH) xor (A) word (A) (A) xor imm16 word (A) (A) xor (ear) word (A) (A) xor (eam) word (ear) (ear) xor (A) word (eam) (eam) xor (A)
A 1 2 A, #imm16 3 2 A, ear 2 3 A, eam 2+ 4+ (a) ear, A 2 3 eam, A 2+ 5+ (a) A 1 2 A, #imm16 3 2 A, ear 2 3 A, eam 2+ 4+ (a) ear, A 2 3 eam, A 2+ 5+ (a) A 1 2 A, #imm16 3 2 A, ear 2 3 A, eam 2+ 4+ (a) ear, A 2 3 eam, A 2+ 5+ (a) 1 2 2 3 2+ 5+ (a)
NOTW A NOTW ear NOTW eam
0 word (A) not (A) 0 word (ear) not (ear) 2x (c) word (eam) not (eam)
Note : For an explanation of "(a)" to "(d)", refer to Table 4, "Number of Execution Cycles for Each Type of Addressing," and Table 5, "Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles."
88
MB90420G/5G (A) Series
Table 15 Mnemonic ANDL A, ear ANDL A, eam ORL ORL A, ear A, eam # 2 2+ 2 2+ 2 2+ ~ 6 7+ (a) 6 7+ (a) 6 7+ (a) Logical 2 Instructions (Long Word) [6 Instructions]
RG
B 0 (d) 0 (d) 0 (d)
Operation long (A) (A) and (ear) long (A) (A) and (eam) long (A) (A) or (ear) long (A) (A) or (eam) long (A) (A) xor (ear) long (A) (A) xor (eam)
LH
AH
I
S
T
N
Z
V
C
RMW
2 0 2 0 2 0
- - - - - -
- - - - - -
- - - - - -
- - - - - -
- - - - - -
* * * * * *
* * * * * *
R R R R R R
- - - - - -
- - - - - -
XORL A, ea XORL A, eam
Note : For an explanation of "(a)" to "(d)", refer to Table 4, "Number of Execution Cycles for Each Type of Addressing," and Table 5, "Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles."
Table 16 Mnemonic NEG NEG NEG A ear eam # 1 ~ 2
Sign Inversion Instructions (Byte/Word) [6 Instructions]
RG
B 0
Operation byte (A) 0 - (A)
LH
AH
I
S
T
N
Z
V
C
RMW
0 2 0 0 2 0
X - - - - -
- - - - - -
- - - - - -
- - - - - -
- - - - - -
* * * * * *
* * * * * *
* * * * * *
* * * * * *
- - * - - *
2 3 2+ 5+ (a) 1 2
0 byte (ear) 0 - (ear) 2x (b) byte (eam) 0 - (eam) 0 word (A) 0 - (A)
NEGW A NEGW ear NEGW eam
2 3 2+ 5+ (a)
0 word (ear) 0 - (ear) 2x (c) word (eam) 0 - (eam)
Note : For an explanation of "(a)" to "(d)", refer to Table 4, "Number of Execution Cycles for Each Type of Addressing," and Table 5, "Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles."
Table 17 Mnemonic NRML A, R0 # 2 ~ *1 RG 1 B 0
Normalize Instruction (Long Word) [1 Instruction] Operation
LH AH I S T N Z V C RMW
long (A) Shift until first digit is "1" - byte (R0) Current shift count
-
-
-
-
-
*
-
-
-
*1: 4 when the contents of the accumulator are all zeroes, 6 + (R0) in all other cases (shift count). Note : For an explanation of "(a)" to "(d)", refer to Table 4, "Number of Execution Cycles for Each Type of Addressing," and Table 5, "Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles."
89
MB90420G/5G (A) Series
Table 18 Mnemonic
RORC A ROLC A RORC ear RORC eam ROLC ear ROLC eam ASR LSR LSL A, R0 A, R0 A, R0
Shift Instructions (Byte/Word/Long Word) [18 Instructions]
RG
# 2 2
~ 2 2
B 0 0
Operation
byte (A) Right rotation with carry byte (A) Left rotation with carry byte (ear) Right rotation with carry byte (eam) Right rotation with carry byte (ear) Left rotation with carry byte (eam) Left rotation with carry
byte (A) Arithmetic right barrel shift (A, R0) byte (A) Logical right barrel shift (A, R0) byte (A) Logical left barrel shift (A, R0) word (A) Arithmetic right shift (A, 1 bit)
LH AH
I
S
T
N
Z
V
C
RMW
0 0
- - - - - - - - - - - - - - -
- - - - - - - - - - - - - - - - - -
--- --- - - - - - - - - - - - -
* * * * * * * * *
* * * * * * * * *
- - - - - - - - - - - - - - - - - -
* * * * * * * * * * * * * * * * * *
- - - * - * - - - - - - - - - - - -
2 3 2+ 5+ (a) 2 3 2+ 5+ (a) 2 2 2 1 1 1 2 2 2 2 2 2 *1 *1 *1 2 2 2 *1 *1 *1 *2 *2 *2
2 0 0 2x (b) 2 0 0 2x (b) 1 1 1 0 0 0 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0
--* --* ---
ASRW A LSRW A/SHRW A LSLW A/SHLW A ASRW A, R0 LSRW A, R0 LSLW A, R0 ASRL A, R0 LSRL A, R0 LSLL A, R0
word (A) Logical right shift (A, 1 bit) word (A) Logical left shift (A, 1 bit)
word (A) Arithmetic right barrel shift (A, R0) word (A) Logical right barrel shift (A, R0) word (A) Logical left barrel shift (A, R0) long (A) Logical right barrel shift (A, R0) long (A) Logical left barrel shift (A, R0)
--*** --*R* ---** --* --* --- --* --* --- * * * * * * * * * * * *
long (A) Arithmetic right shift (A, R0) -
- -
*1: 6 when R0 is 0, 5 + (R0) in all other cases. *2: 6 when R0 is 0, 6 + (R0) in all other cases. Note : For an explanation of "(a)" to "(d)", refer to Table 4, "Number of Execution Cycles for Each Type of Addressing," and Table 5, "Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles."
90
MB90420G/5G (A) Series
Table 19 Mnemonic BZ/BEQ BNZ/BNE BC/BLO BNC/BHS BN rel BP rel BV rel BNV rel BT rel BNT rel BLT rel BGE rel BLE rel BGT rel BLS rel BHI rel BRA rel JMP JMP JMP JMP JMPP JMPP JMPP CALL CALL CALL CALLV CALLP rel rel rel rel # 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 1 3 2 2+ 2 2+ 4 ~ * *1 *1 *1 *1 *1 *1 *1 *1 *1 *1 *1 *1 *1 *1 *1 *1 2 3 3 4+ (a) 5 6+ (a) 4 6 7+ (a) 6 7 10
1
Branch 1 Instructions [31 Instructions] B 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (c) 0 (d) 0 Operation Branch when (Z) = 1 Branch when (Z) = 0 Branch when (C) = 1 Branch when (C) = 0 Branch when (N) = 1 Branch when (N) = 0 Branch when (V) = 1 Branch when (V) = 0 Branch when (T) = 1 Branch when (T) = 0 Branch when (V) xor (N) = 1 Branch when (V) xor (N) = 0
Branch when ((V) xor (N)) or (Z) = 1 Branch when ((V) xor (N)) or (Z) = 0
LH AH I S T N Z V C RMW
RG
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 2 0 0 1 0 0 0 2 0 0
Branch when (C) or (Z) = 1 Branch when (C) or (Z) = 0 Branch unconditionally word (PC) (A) word (PC) addr16 word (PC) (ear) word (PC) (eam)
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
@A addr16 @ear @eam @ear *3 @eam *3 addr24
word (PC) (ear), (PCB) (ear +2) word (PC) (eam), (PCB) (eam +2)
2 @ear *4 @eam *4 2+ addr16 *5 3 1 #vct4 *5 2 @ear *6
(c) 2x (c) (c) 2x (c) 2x (c) *2 2x (c)
CALLP @eam *6 CALLP addr24 *7 *1: *2: *3: *4: *5: *6: *7:
2+ 11+ (a) 4 10
word (PC) ad24 0 to 15, (PCB) ad24 16 to 23 word (PC) (ear) word (PC) (eam) word (PC) addr16 Vector call instruction word (PC) (ear) 0 to 15, (PCB) (ear) 16 to 23 word (PC) (eam) 0 to 15, (PCB) (eam) 16 to 23 word (PC) addr0 to 15, (PCB) addr16 to 23
4 when branching, 3 when not branching. (b) + 3 x (c) Read (word) branch address. W: Save (word) to stack; R: read (word) branch address. Save (word) to stack. W: Save (long word) to W stack; R: read (long word) R branch address. Save (long word) to stack.
Note : For an explanation of "(a)" to "(d)", refer to Table 4, "Number of Execution Cycles for Each Type of Addressing," and Table 5, "Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles."
91
MB90420G/5G (A) Series
Table 20 Mnemonic CBNE A, #imm8, rel CWBNE A, #imm16, rel CBNE
CBNE
Branch 2 Instructions [19 Instructions] B 0 0 0 (b) 0 (c) 0 Operation
Branch when byte (A) imm8 Branch when word (A) imm16 Branch when byte (ear) imm8 Branch when byte (eam) imm8 Branch when word (ear) imm16 Branch when word (eam) imm16
LH AH I S T N Z V C RMW
# 3 4
10
~ * *1 *2 *3 *4 *3 *5
1
RG
0 0 1 0 1 0 2
- - - - - - - - - - - - - - - -
----* ----* - - - - - - - - - - - - - - - - * * * *
* * * * * * * * * * - - - - *
* * * * * *
* * * * * *
- - - - - - - * - * - - - - - -
ear, #imm8, rel
eam, #imm8, rel*
CWBNE ear, #imm16, rel
CWBNE eam, #imm16, rel*10
4 4+ 5 5+ 3
DBNZ DBNZ
ear, rel eam, rel
3+ *6 3 *5
Branch when byte (ear) = (ear) - 1, and (ear) 0 2 2x (b) Branch when byte (eam) = (eam) - 1, and (eam) 0 2 2 0 0 0 0 0 0 Branch when word (ear) = (ear) - 1, and (ear) 0 2x (c) Branch when word (eam) = (eam) - 1, and (eam) 0 8x (c) 6x (c) 6x (c) 8x (c) *7 (c) Software interrupt Software interrupt Software interrupt Software interrupt Return from interrupt At constant entry, save old frame pointer to stack, set new frame pointer, and allocate local pointer area At constant entry, retrieve old frame pointer from stack. Return from subroutine Return from subroutine 0
----* ----* ----* ----* - - - - - R R R R * S S S S * - - - - * - - - - *
*- *- *- *- - - - - * - - - - *
DWBNZ ear, rel DWBNZ eam, rel INT INT INTP INT9 RETI LINK #vct8 addr16 addr24
3+ *6 2 3 4 1 1 2 20 16 17 20 15 6
#imm8
--------
UNLINK RET *8 RETP *9
1 1 1
5 4 6
0 0 0
(c) (c) (d)
- - -
-------- -------- --------
- - -
*1: 5 when branching, 4 when not branching *2: 13 when branching, 12 when not branching *3: 7 + (a) when branching, 6 + (a) when not branching *4: 8 when branching, 7 when not branching *5: 7 when branching, 6 when not branching *6: 8 + (a) when branching, 7 + (a) when not branching *7: Set to 3 x (b) + 2 x (c) when an interrupt request occurs, and 6 x (c) for return. *8: Retrieve (word) from stack *9: Retrieve (long word) from stack *10: In the CBNE/CWBNE instruction, do not use the RWj+ addressing mode. Note : For an explanation of "(a)" to "(d)", refer to Table 4, "Number of Execution Cycles for Each Type of Addressing," and Table 5, "Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles."
92
MB90420G/5G (A) Series
Table 21 Mnemonic PUSHW A PUSHW AH PUSHW PS PUSHW rlst POPW POPW POPW POPW JCTX A AH PS rlst @A # 1 1 1 2 1 1 1 2 1 2 2 2 2 Other Control Instructions (Byte/Word/Long Word) [28 Instructions] ~ 4 4 4 *3 3 3 4 *2 14 3 3 2 2
RG
B (c) (c) (c) *4 (c) (c) (c) *4
Operation
word (SP) (SP) -2, ((SP)) (A) word (SP) (SP) -2, ((SP)) (AH) word (SP) (SP) -2, ((SP)) (PS) (SP) (SP) -2n, ((SP)) (rlst) word (A) ((SP)), (SP) (SP) +2 word (AH) ((SP)), (SP) (SP) +2 word (PS) ((SP)), (SP) (SP) +2 (rlst) ((SP)), (SP) (SP) +2n
LH AH
I
S
T
N
Z
V
C
RMW
0 0 0 *5 0 0 0 *5 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0
- - - - - - - - -
- - - - * - - - - - - - - - - * * - -
- - - -
- - - -
- - - -
- - - -
- - - -
- - - -
- - - -
- - - - - - - - - - - - - - - - - - - - - - - - - - - -
------- ------- ******* ------- * * * * * * * * * * * * * * * * * * * * *
6x (c) Context switch instruction 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
AND CCR, #imm8 OR CCR, #imm8 MOV RP #imm8 , MOV ILM, #imm8
byte (CCR) (CCR) and imm8 - - byte (CCR) (CCR) or imm8 byte (RP) imm8 byte (ILM) imm8 word (RWi) ear word (RWi) eam word(A) ear word (A) eam word (SP) (SP) +ext (imm8) word (SP) (SP) +imm16 byte (A) (brgl) byte (brg2) (A) No operation
Prefix code for accessing AD space Prefix code for accessing DT space Prefix code for accessing PC space Prefix code for accessing SP space
- - - - - - - -
------- ------- - - - - - - - - - - - - - - - - - - - - - - - - - - - -
MOVEA RWi, ear 2 3 MOVEA RWi, eam 2+ 2+ (a) MOVEA A, ear 2 1 MOVEA A, eam 2+ 1+ (a) ADDSP #imm8 ADDSP #imm16 MOV MOV NOP ADB DTB PCB SPB NCC CMR A, brgl brg2, A 2 3 2 2 1 1 1 1 1 1 1 3 3 *1 1 1 1 1 1 1 1 1
------- ------- --- --- - - - - - - - - - - - - - - - - - - - - - * * - - - - - - - * * - - - - - - - -- -- - - - - - - - - - - - - - -
Z* -- - - - - - - - - - - - - - -
Prefix code for no flag change
Prefix code for common register bank
*1: PCB, ADB, SSB, USB, and SPB : 1 state DTB, DPR : 2 states *2: 7 + 3 x (pop count) + 2 x (last register number to be popped), 7 when rlst = 0 (no transfer register) *3: 29 +3 x (push count) - 3 x (last register number to be pushed), 8 when rlst = 0 (no transfer register) *4: Pop count x (c), or push count x (c) *5: Pop count or push count. Note : For an explanation of "(a)" to "(d)", refer to Table 4, "Number of Execution Cycles for Each Type of Addressing," and Table 5, "Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles."
93
MB90420G/5G (A) Series
Table 22 Mnemonic MOVB A, dir:bp MOVB A, addr16:bp MOVB A, io:bp MOVB dir:bp, A MOVB addr16:bp, A MOVB io:bp, A SETB dir:bp SETB addr16:bp SETB io:bp CLRB dir:bp CLRB addr16:bp CLRB io:bp BBC BBC BBC BBS BBS BBS dir:bp, rel addr16:bp, rel io:bp, rel dir:bp, rel addr16:bp, rel io:bp, rel # 3 4 3 3 4 3 3 4 3 3 4 3 4 5 4 4 5 4 5 3 3 ~ 5 5 4 7 7 6 7 7 7 7 7 7 *1 *1 *2 *1 *1 *2 *3 *4 *4
RG
Bit Manipulation Instructions [21 Instructions] B (b) (b) (b) Operation byte (A) (dir:bp) b byte (A) (addr16:bp) b byte (A) (io:bp) b
LH AH I S T N Z V C RMW
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Z Z Z - - - - - - - - - - - - - - - - - -
* * * - - - - - - - - - - - - - - - - - -
- - - - - - - - - - - - - - - - - - - - -
- - - - - - - - - - - - - - - - - - - - -
- - - - - - - - - - - - - - - - - - - - -
* * * * * * - - - - - - - - - - - - - - -
* * * * * * - - - - - - * * * * * * * - -
- - - - - - - - - - - - - - - - - - - - -
- - - - - - - - - - - - - - - - - - - - -
- - - * * * * * * * * * - - - - - - * - -
2x (b) bit (dir:bp) b (A) 2x (b) bit (addr16:bp) b (A) 2x (b) bit (io:bp) b (A) 2x (b) bit (dir:bp) b 1 2x (b) bit (addr16:bp) b 1 2x (b) bit (io:bp) b 1 2x (b) bit (dir:bp) b 0 2x (b) bit (addr16:bp) b 0 2x (b) bit (io:bp) b 0 (b) (b) (b) (b) (b) (b) 2x (b) *5 *5 Branch when (dir:bp) b = 0 Branch when (addr16:bp) b = 0 Branch when (io:bp) b = 0 Branch when (dir:bp) b = 1 Branch when (addr16:bp) b = 1 Branch when (io:bp) b = 1
Branch when (addr16:bp) b = 1, bit = 1
SBBS addr16:bp, rel WBTS io:bp WBTC io:bp *1: *2: *3: *4: *5:
Wait until (io:bp) b = 1 Wait until (io:bp) b = 0
8 when branching, 7 when not branching 7 when branching, 6 when not branching 10 when condition is satisfied, 9 when not satisfied Undefined count Until condition is satisfied
Note : For an explanation of "(a)" to "(d)", refer to Table 4, "Number of Execution Cycles for Each Type of Addressing," and Table 5, "Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles." Table 23 Mnemonic SWAP SWAPW/XCHW A,T EXT EXTW ZEXT ZEXTW Accumulator Manipulation Instructions (Byte/Word) [6 Instructions] # 1 1 1 1 1 1 ~ 3 2 1 2 1 1
RG
B 0 0 0 0 0 0
Operation byte (A) 0 to 7 (A) 8 to 15 word (AH) (AL) byte sign extension word sign extension byte zero extension word zero extension
LH
AH
I
S
T
N
Z
V
C
RMW
0 0 0 0 0 0
- - X - Z -
- * - X - Z
- - - - - -
- - - - - -
- - - - - -
- - * * R R
- - * * * *
- - - - - -
- - - - - -
- - - - - -
Note: For an explanation of "(a)" to "(d)", refer to Table 4, "Number of Execution Cycles for Each Type of Addressing," and Table 5, "Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles."
94
MB90420G/5G (A) Series
Table 24 Mnemonic MOVS/MOVSI MOVSD SCEQ/SCEQI SCEQD FISL/FILSI # 2 2 2 2 ~ * *2 *1 *1
2
String Instructions [10 Instructions] Operation
LH AH I S T N Z V C RMW
RG
B * *3 *4 *4 *3 *6 *6 *7 *7 *6
3
* *5 *5 *5
5
Byte transfer @AH+ @AL+, counter = RW0 Byte transfer @AH- @AL-, counter = RW0 Byte retrieval (@AH+) - AL, counter = RW0 Byte retrieval (@AH-) - AL, counter = RW0 Byte filling @AH+ AL, counter = RW0 Word transfer @AH+ @AL+, counter = RW0 Word transfer @AH- @AL-, counter = RW0 Word retrieval (@AH+) - AL, counter = RW0 Word retrieval (@AH-) - AL, counter = RW0 Word filling @AH+ AL, counter = RW0
- - - - - - - - - -
- - - - - - - - - -
- - - - - - - - - -
- - - - - - - - - -
- - - - - - - - - -
- - * * * - - * * *
- - * * * - - * * *
- - * * - - - * * -
- - * * - - - * * -
- - - - - - - - - -
2 6m +6 *5 *2 *2 *1 *1 *8 *8 *8 *8
MOVSW/MOVSWI 2 MOVSWD 2 SCWEQ/SCWEQI SCWEQD FILSW/FILSWI 2 2
2 6m +6 *8
m: RW0 value (counter value) n: Loop count *1: 5 when RW0 is 0, 4 + 7 x (RW0) for count out, and 7 x n + 5 when match occurs *2: 5 when RW0 is 0, 4 + 8 x (RW0) in any other case *3: (b) x (RW0) + (b) x (RW0) when accessing different areas for the source and destination, calculate (b) separately for each. *4: (b) x n *5: 2 x (RW0) *6: (c) x (RW0) + (c) x (RW0) when accessing different areas for the source and destination, calculate (c) separately for each. *7: (c) x n *8: 2 x (RW0) Note : For an explanation of "(a)" to "(d)", refer to Table 4, "Number of Execution Cycles for Each Type of Addressing," and Table 5, "Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles."
95
MB90420G/5G (A) Series
s ORDERING INFORMATION
Part number MB90F428GAPF MB90F423GAPF MB90428GAPF MB90427GAPF MB90423GAPF MB90F428GPF MB90F423GPF MB90428GPF MB90427GPF MB90423GPF MB90F428GAPFV MB90F423GAPFV MB90428GAPFV MB90427GAPFV MB90423GAPFV MB90F428GPFV MB90F423GPFV MB90428GPFV MB90427GPFV MB90423GPFV Package Remarks
Plastic QFP, 100-pin (FPT-100P-M06)
Plastic LQFP, 100-pin (FPT-100P-M05)
96
MB90420G/5G (A) Series
s PACKAGE DIMENSIONS
Plastic QFP, 100-pin (FPT-100P-M06)
23.900.40(.941.016) 20.000.20(.787.008)
80 81 51 50
3.35(.132)MAX (Mounting height) 0.05(.002)MIN (STAND OFF)
14.000.20 (.551.008)
INDEX
100 31
17.900.40 (.705.016)
12.35(.486) REF
16.300.40 (.642.016)
"A" LEAD No.
1 30
0.65(.0256)TYP
0.300.10 (.012.004)
0.13(.005)
M
0.150.05(.006.002)
Details of "A" part 0.25(.010) "B" 0.10(.004) 18.85(.742)REF 22.300.40(.878.016) 0.30(.012) 0.18(.007)MAX 0.53(.021)MAX Details of "B" part
0
10
0.800.20 (.031.008)
C
1994 FUJITSU LIMITED F100008-3C-2
Dimensions in mm (inches)
(Continued)
97
MB90420G/5G (A) Series
(Continued) Plastic LQFP, 100-pin (FPT-100P-M05)
16.000.20(.630.008)SQ
75
1.50 -0.10
51
+0.20 +.008
(Mouting height)
14.000.10(.551.004)SQ
.059 -.004
76
50
12.00 (.472) REF INDEX
15.00 (.591) NOM
Details of "A" part 0.15(.006)
100
26
0.15(.006) 0.15(.006)MAX
LEAD No.
1
25
"B"
+0.05 +.002
"A" 0.50(.0197)TYP 0.18 -0.03 .007 -.001
+0.08 +.003
0.40(.016)MAX 0.127 -0.02 .005 -.001
0.08(.003)
M
Details of "B" part 0.100.10 (STAND OFF) (.004.004)
0.10(.004)
0.500.20(.020.008) 0~10
C
1995 FUJITSU LIMITED F100007S-2C-3
Dimensions in mm (inches)
98
MB90420G/5G (A) Series
FUJITSU LIMITED
For further information please contact: Japan FUJITSU LIMITED Corporate Global Business Support Division Electronic Devices Shinjuku Dai-Ichi Seimei Bldg. 7-1, Nishishinjuku 2-chome, Shinjuku-ku, Tokyo 163-0721, Japan Tel: +81-3-5322-3347 Fax: +81-3-5322-3386 http://edevice.fujitsu.com/ North and South America FUJITSU MICROELECTRONICS, INC. 3545 North First Street, San Jose, CA 95134-1804, U.S.A. Tel: +1-408-922-9000 Fax: +1-408-922-9179 Customer Response Center Mon. - Fri.: 7 am - 5 pm (PST) Tel: +1-800-866-8608 Fax: +1-408-922-9179 http://www.fujitsumicro.com/ Europe FUJITSU MICROELECTRONICS EUROPE GmbH Am Siebenstein 6-10, D-63303 Dreieich-Buchschlag, Germany Tel: +49-6103-690-0 Fax: +49-6103-690-122 http://www.fujitsu-fme.com/ Asia Pacific FUJITSU MICROELECTRONICS ASIA PTE. LTD. #05-08, 151 Lorong Chuan, New Tech Park, Singapore 556741 Tel: +65-281-0770 Fax: +65-281-0220 http://www.fmap.com.sg/ Korea FUJITSU MICROELECTRONICS KOREA LTD. 1702 KOSMO TOWER, 1002 Daechi-Dong, Kangnam-Gu,Seoul 135-280 Korea Tel: +82-2-3484-7100 Fax: +82-2-3484-7111
All Rights Reserved. The contents of this document are subject to change without notice. Customers are advised to consult with FUJITSU sales representatives before ordering. The information and circuit diagrams in this document are presented as examples of semiconductor device applications, and are not intended to be incorporated in devices for actual use. Also, FUJITSU is unable to assume responsibility for infringement of any patent rights or other rights of third parties arising from the use of this information or circuit diagrams. The contents of this document may not be reproduced or copied without the permission of FUJITSU LIMITED. FUJITSU semiconductor devices are intended for use in standard applications (computers, office automation and other office equipments, industrial, communications, and measurement equipments, personal or household devices, etc.). CAUTION: Customers considering the use of our products in special applications where failure or abnormal operation may directly affect human lives or cause physical injury or property damage, or where extremely high levels of reliability are demanded (such as aerospace systems, atomic energy controls, sea floor repeaters, vehicle operating controls, medical devices for life support, etc.) are requested to consult with FUJITSU sales representatives before such use. The company will not be responsible for damages arising from such use without prior approval. Any semiconductor devices have inherently a certain rate of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign Exchange and Foreign Trade Control Law of Japan, the prior authorization by Japanese government should be required for export of those products from Japan.
F0012 (c) FUJITSU LIMITED Printed in Japan

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